Analog Computing Technologies and Circuits for Efficient Machine Learning Hardware
Organizer: Arindam Mallik (imec) and Nadine Collaert (imec)
The purpose of the workshop is to outline the challenges and novel solutions to implement analog computing for machine learning (ML) hardware. Deep Neural Networks (DNN) constitute the state-of-the-art in AI, from image processing to translation and speech recognition. Energy-efficient DNN is key to bringing these capabilities to edge devices. Analog in-Memory Computing (AiMC) using novel technologies such as RRAM, PCM, MRAM is gaining a large interest due to superb energy-efficiency. However, implementation of AiMC in a primarily digital system brings new challenges that range from device specifications to system architecture definition. The objective of this workshop is to share innovations at both technology and design space to enable system-technology co-optimization for ML hardware.
- The workshop will provide a comprehensive and concise overview of the field of analog computing for ML.
- Novel technology solutions (memory and logic devices) that are optimized for executing ML inference algorithm in the hardware.
- Co-optimization of ML algorithm and system architecture to reduce the memory bottleneck and power consumption\
- This workshop establishes the close interaction between the design and device technology community needed for optimal solution for ML hardware.
Speakers and Presentations:
- Boris Murmann, Stanford University – “Prospects of Analog In-Memory Computing – An Overview” (30 min)
- Robert L. Bruce, IBM Research – “Designing Material Systems and Algorithms for Analog Computing” (30 min)
- Jae-sun Seo, Arizona State University – “Monolithically Integrated RRAM-based Analog/ Mixed-Signal In-Memory Computing for Energy-Efficient Deep Learning” (30 min)
- Jaydeep Kulkarni, University of Texas at Austin – “Compute-in-Memory Circuit and Device Technologies: Trends and Prospects” (30 min)
- Arindam Mallik, imec – “Analog Computing for Machine Learning – An Ideal Case for Co-Optimization of System and Device Technology” (30 min)
- Mahesh Mehendale, Texas Instruments – “System and Architecture Level Considerations in Leveraging Mixed-Signal Techniques for ML at the Edge” (30 min)
Know Where You Are Going; Metrology In the New Age of Semiconductor Manufacturing
Organizers: Tom Larson (Nova Measuring Instruments) and Gosia Jurczak (Lam Research)
Abstract: Measurement is at the forefront of every integration and process engineer’s daily life, whether for process control, development, yield ramping or failure analysis. But understanding the basics of how the measurements are made, what technologies are deployed and what challenges remain is not universal. This workshop will provide an outline overview from world class experts of the major technologies and approaches used now and looking into the future of inspection, process control and analysis. The overview sessions will provide the attendee with an understanding of how measurement data is produced, how it is used and how measurements solve critical problems every day. The agenda will span several talks from experts in the fab as well as experts from the fields of dimensional measurements, materials metrology, defect inspection and laboratory analysis including discussion around how machine learning is enhancing what we can extract from the data. The organizers hope the attendees will leave the workshop with a more robust understanding of how their measurement data is created and perhaps with a better understanding of how to use the data.
The agenda will be 2.5 hours long. It will start with an overview of challenges from logic and memory. Then there will be a focal talk from each of the categories: Inspection, Dimensional metrology, Materials metrology, Analytical Lab
Speakers and Presentations:
- Tom Larson, Nova Measuring Instruments – “Introduction to Metrology Workshop”
- Keiji Suzuki, Kioxia Corporation – “Manufacturing Process Challenges and Requirements for Metrology in Semiconductor Memory Devices”
- Yi Hung Lin, TSMC – “Metrology with Angstrom Accuracy Required by Logic IC Manufacturing – Challenges From R&D to High Volume Manufacturing and Solutions in the AI Era”
- Philippe Leray, imec – “Dimensional Metrology Overview, Trends and Upcoming Challenges”
- Mark Shirey, KLA – “Defect Inspection: A Trio of Trends for the 2020s”
- Kavita Shah, Nova Measuring Instruments – “Enabling Modern Semiconductor Manufacturing With Materials Metrology”
- Markus Kuhn, Intel – “Opportunities and Challenges for Lab-based Characterization for Emerging Technologies”
Quantum Computing for Electrical Engineers
Organizer: Iuliana Radu (IMEC) and Maud Vinet (CEA Leti)
This workshop is going to outline the state of the art of quantum computing from material and integration to IC design and architecture and system. We will discuss and argue how quantum computing could be supported by our electrical engineering community and could provide a very aggressive path towards dedicated high performance computing problems. Through the workshop, we will try to provide a comprehensive and concise overview of the field of quantum computing enabled by VLSI technology.
The total duration of the workshop will be 2h30.
Speakers and Presentations:
William Oliver, Massachusetts Institute of Technology – “3D Integration and Challenges for Scaling”
Doug McClure, IBM – “Superconducting Qubits: How Technology/ Processing/ Materials Impact Coherence Time and How Design Impacts Gate Fidelity”
Iuliana Radu, imec – “Si Based Qubits: Technology and Material Impact on Performance”
Maud Vinet, CEA-Leti – “Architectures Challenges for Si Spin Qubits”
Joseph Bardin, Google AI Quantum & University of Massachusetts Amherst – “Cryogenic CMOS for Control of Transmon Qubits”