Workshop 3

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Deep Analysis Can Compress the Time to Design Optimum Analog/Mixed-Signal Circuits

Organizers: Asad A. Abidi (University of California Los Angeles) and Tetsuya Iizuka (The University of Tokyo)

The automatic synthesis of analog circuits is a long-held dream that, despite many efforts, has not materialized so far. The analog portions of modern systems-on-a-chip are often the bottleneck in design time and rely upon specialized expertise that is frequently in short supply. Migration to new technology nodes is also hugely labour-intensive.
Recent advances in the design-oriented analysis and abstraction of commonly used analog circuits and subsystems are proving to be reliable and efficient in speeding up the design of complex subsystems, such as high-resolution data converters, to a few days. What is meant here by “design” is: a choice of the best among competing architectures or topologies, and the definition of key circuits down to a first cut at FET sizes. The choices guarantee optimum performance, for example, for a given power consumption in a specified technology.
An execution phase must necessarily follow. Time-consuming circuit simulation is used to check correctness, robustness to PVT variations, and sensitivity to layout parasitics. But this phase is guided, and accelerated, by the a priori knowledge of the optimum architecture and circuits as obtained in the first step.

About Asad A. Abidi

Asad A. Abidi received the B.Sc. degree (with honors) from Imperial College, London, U.K., in 1976 and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1978 and 1981, respectively. From 1981 to 1984, he was with Bell Laboratories, Murray Hill, NJ. Since 1985, he has been with the Electrical Engineering Department, University of California, Los Angeles, where he is Distinguished Chancellor’s Professor. His research interests span fundamentals of circuit design, RF CMOS circuits, high-speed analog circuits, and data conversion.
He received the 2008 IEEE Solid-State Circuit Society’s Donald O. Pederson Award. He has been elected Fellow of IEEE, Member of the US National Academy of Engineering, and Fellow of TWAS-the world academy of sciences.

About Tetsuya Iizuka

Tetsuya Iizuka received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2002, 2004, and 2007, respectively. From 2007 to 2009, he was with THine Electronics Inc., Tokyo, Japan, as a high-speed serial interface circuit engineer.
He joined the University of Tokyo in 2009, where he is currently an Associate Professor with Systems Design Lab., School of Engineering. From 2013 to 2015, he was a Visiting Scholar with the University of California, Los Angeles, CA, USA. His current research interests include data conversion techniques, high-speed analog integrated circuits, digitally-assisted analog circuits and VLSI computer-aided design.

Live Session: June 13, 7:00 AM-9:00AM (JST)

• 7:00 – 7:10  Introduction (Prof. Asad Abidi)
• 7:10 – 7:15  Elevator Pitch 1 (Prof. Willy Sansen)
• 7:15 – 7:25  Q&A session for 1st talk
• 7:40 – 7:45  Elevator Pitch 2 (Dr. Kejian Shi)
• 7:45 – 7:55  Q&A session for 2nd talk
• 7:55 – 8:00  Elevator Pitch 3 (Dr. Dihang Yang)
• 8:00 – 8:10  Q&A session for 3rd talk
• 8:10 – 8:15  Elevator Pitch 4 (Prof. Shanthi Pavan)
• 8:15 – 8:25  Q&A session for 4th talk
• 8:25 – 8:30  Elevator Pitch 5 (Prof. Tetsuya Iizuka)
• 8:30 – 8:40  Q&A session for 5th talk
• 8:40 – 9:00   Panel Discussion

1. Optimum Opamp Design in One Day, Willy Sansen, KU Leuven

In the design of operational amplifiers, the focus is on the conversion of power into high Gain-Bandwidth and low noise. In single-stage amplifiers, the only free design variables are the biasing voltage and the channel length. In two-stage operational amplifiers however, stability is the main concern. A compensation capacitance can be inserted, or feedforward can be used. In three-stage amplifiers pole-zero compensation needs to be involved, which yields superior power efficiencies. Design plans are given for all three of them, in present and future nanometer CMOS technologies. Since such op amp design is based on analytical expressions, it is probably optimum for its specifications.

2. Wireless Receiver Front-End Design, Kejian Shi, Broadcom

Multi-band receivers suffer interference from blockers in a multitude of conditions, including leakage from their own transmitter when operating in FDD. The receiver circuits are desired to handle unfiltered blockers that might corrupt the small wanted signal due to nonlinearity. In the mixer-first receiver, the received spectrum at the antenna is immediately shifted to baseband, where the blocker is filtered. Both mixer and baseband filter can play roles on overall receiver linearity. This talk will include the deep design analysis of a passive mixer on small and large signal linearity, and the design methodology of a single-opamp 2nd-order transimpedance amplifier for the mixer-first receiver. The design analysis aims to suggest a solution to speed up optimal design.

3. Frequency Synthesizer Design in Two Days, Dihang Yang, Broadcom

What PLL architectures should we use? What loop bandwidth should we choose? How do we specify the performance for the critical blocks of PLL, such as the oscillator, the phase detector, and the frequency divider? Given the performance requirements, how do we design the circuits? In designing a frequency synthesizer, we often have those questions. Lack of clear answers can easily lead to overdesign or even failure. This talk will provide useful analytical tools to answer these questions. As an example, it will show the development of one synthesizer circuit that illustrates how those tools can lead to an optimal design in a very short time.

4. Delta-Sigma A/D Converter Design, Shanthi Pavan, IIT Madras

The design on a delta-sigma converter intended to achieve a given SNDR over a specified bandwidth opens up a plethora of possibilities. What oversampling ratio should one use? What order and shape of the noise-transfer function should one choose? What about the number of quantization levels? How should the loop filter be configured? What kind of integrators should one employ? This curse of "too many choices", with each path presenting its own set of advantages and drawbacks, often send a designer into a tizzy. The cause is not helped by the many published converters demonstrating excellent performance - each pulling in its own orthogonal direction. This talk aims to cut the clutter and suggests design choices and a methodology that gets a designer close to an "optimal" solution.

5. Nyquist A/D Converter Design in Four Days, Tetsuya Iizuka, The University of Tokyo

As data converters find their way into virtually every microelectronic device, developers of application-specific systems-on-a-chip increasingly suffer from large development costs, arising from limited specialized design expertise and the tedious process of migration to new technology nodes.
In this talk we introduce three pieces of analysis for the optimum design of key building blocks in the ADC: a) Distortion and bandwidth of a passive sample and hold (S/H) circuit, b) noise and offset of a regenerative comparator and c) jitter analysis for a clock distribution path. By deploying these analysis tools, a systematic design framework of ADCs is demonstrated with the optimized design of a self-timed charge-redistribution SAR ADC.