Workshop 2

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PPAC Analysis and System-Technology Co-Optimization for 3D Memory-on-Logic IC, Many-Core SOC and AI Computing Applications

Organizers: Rongmei Chen (imec) and Geert Van der Plas (imec)

In this workshop, the state-of-the-art of 3D IC technology, design techniques and application will be given. Wafer by wafer and face to face hybrid bonding based fine-pitch (<1µm) 3D interconnects will be reviewed and its application to various 3D IC designs will be introduced. 3D partitioning in various levels of caches for applications ranging from mobile SOC to high performance SOC will be evaluated and traded off for system power, performance, area and cost (PPAC) considering the impact of the 3D interconnect technologies. The purpose of this workshop is to provide a comprehensive view of 3D IC design, PPAC analysis, and optimization from technology, circuit, up to system applications. We will cover various studies related to 3D stacking ranging from high-performance 3D CPU physical design, novel 3D microarchitecture exploration to many-core 3D system design, supported by power delivery and thermal analysis. We will supplement these explorations with hardware measurements from a state-of-the-art 3D demonstrator consisting of a cache coherent interconnect mesh implemented in 3D using sub-10µm 3D pitch and face-to-face hybrid wafer bonding technology on 12nm FinFET process node. 3D opportunities to AI computing will also be discussed.

Live Session: June 13, 7:00 AM-9:00AM (JST)

About Rongmei Chen

Rongmei Chen obtained Bachelor and Ph.D. degrees (with excellent Ph.D. thesis honor) from Tsinghua University, China, in 2012 and 2017 respectively. He was awarded with "Ten Best Progress in Radiation Physics Field of China in 2015-2017" for his innovative contribution to the field of radiation effects of IC. He was a post-doc at LIRMM-CNRS/Montpellier University, France from 2017 to 2019. He joined imec, Leuven, Belgium in 2019. He has been working on 3D IC design and exploration, SRAM design, CNT electronics and IC radiation effects. He is currently a research scientist at imec and is also a Marie Curie scholar. He has published more than 30 papers in journals or conferences including TED, TNS, NSREC, RADECS, IEDM etc. He has served as TPC members for several meetings such as VLSI-SOC, EDTM etc..

About Geert Van der Plas

Geert Van der Plas obtained Ph.D. degree from the Katholieke Universiteit Leuven, Belgium, in 2001. He joined imec, Belgium, in 2003. He has been working on energy efficient data converter, power/signal integrity and 3D integration technologies. Currently he is program manager in the 3D system integration program addressing system scaling using advanced 3D (TSV) and packaging (FO-WLP) technology for high performance, mobile and IoT applications. His interests are in characterization, modeling, system exploration and design enablement of 3D integration technologies.

1. Time Performance Improvement by Agile Design and 3D Integration, Tadahiro Kuroda, The University of Tokyo

Abstract:
TBD

2. Future of HBM Packaging Technology, Kangwook Lee, SK hynix

Abstract:
TBD

3. High-Performance AI Computing and 3D Opportunities, Mustafa Badaroglu, Qualcomm

Abstract:
TBD

4. Architecture, Physical Design and 3D Technology Co-Optimization for Next Generation High Performance Energy Efficient Systems, Brian Cline, Arm

Abstract:
TBD

5. 3D Partitioning Strategies for Memory-on-Logic Designs for Many Core SoCs, Dragomir Milojevic, Universite Libre de Bruxelles

Abstract:
TBD

6. Entering a New Dimension with 3D-IC Design, Vinay Patwardhan, CADENCE

Abstract:
TBD

7. 3D Technology: the Enabler for Advanced Digital Applications, Francois Andrieu, CEA-Leti

Abstract:
TBD

8. Tackling the Memory Wall via 3D Memory Partitioning - A System Level Perspective, Manu Perumkunnil, imec

Abstract:
TBD