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Technology Short Courses

Future of Scaling for Logic and Memory

Abstract: Horizontally stacked GAA Nanosheet structures can answer logic device needs for future technologies. They offer excellent electrostatics and short channel control, can be fabricated with minimal deviation from FinFET, with a significant reuse of legacy integration and manufacturing knowledge, and circumvent some of the patterning challenges associated with scaled technologies. Additionally, NS device architecture enable the best CMOS logic power and performance trade-off and provide additional area and gate length (Lg) scaling benefits at the 5nm node and beyond. The improved electrostatics of GAA devices and additional design flexibility, which allow a continuous range of active widths (Weff) in Nanosheet devices, open new opportunities in term of power/performance optimization. The benefits of using this technology for mobile and High Performance applications, including specific process and performance elements will be discussed. The challenges associated with the fabrication and the maturity of this technology for high volume manufacturing will be also discussed.

Bio: Nicolas Loubet received the B.S. and M.S. degrees in physics from Paul Sabatier University, Toulouse, France, in 2000 and 2001. In 2003, he received a high-level engineering degree in the field of physics and microelectronics from the National Institute of Applied Sciences in Toulouse, and the Ph.D. degree in 2006. From 2003 to 2008, he joined STMicroelectronics R&D group in front-end materials and epitaxy where he developed advanced epitaxy of Si and SiGe materials, and HCl vapor-phase etching of SiGe for the fabrication of silicon-on-nothing and dielectric isolation transistors. In 2008, he joined the Silicon Technology Research Alliance at IBM Research in Albany, NY and focused on junction and strain module engineering for the 20nm to 7nm CMOS device nodes using strained SOI and SGOI, SiGe relaxed buffer, and ultra-low resistivity SiGe:B and SiC:P for FDSOI and FinFET devices on bulk and SOI substrates. In 2015, he became a Senior Engineer and Technical Leader at IBM Research where his research focused on material, process, and device integration of Gate-All-Around devices for 5nm CMOS technology and beyond. He currently manages the Front-End Of Line (FEOL) Process Development team at IBM Research focusing on leading edge CMOS logic devices. He has published more than 100 papers and more than 250 patents.

Abstract: Interconnects advancements are critical to enabling Moore’s law. Each technology node demands: (1) pitch scaling at the lower metal layers to enable cell area reduction; (2) increasing number of interconnect layers; and (3) improvements in capacitance, line and via resistance on all layers (performance). In addition, 3D integration trends, including die and wafer stacking, create new challenges and open new opportunities. Future scaling research paths that include device stacking and novel power distribution schemes bring about need for additional interconnect advancements. In parallel, the impact of interconnects on overall part performance generates increased attention and visibility to interconnects. These ongoing trends have made Interconnect research one of the most dynamic and exciting areas in the Semiconductor Industry, abundant with exciting new ideas, challenges and opportunities. In this short course, we will first review the basic geometries, performance needs, and scaling trends of interconnects. We will also highlight a few of the most significant advances in the past 20 years. We will then discuss the most exciting leading options that Industry and Academia are exploring for future technology nodes. For scaling to 20 nm pitch and below, we will cover subtractive interconnects, new material options, and patterning techniques for shorting margin, such as self-alignment techniques and selective deposition. For mid-pitch intermediate layers, we will cover progress on three methods to improve performance: i) barrier/liner thinning (standard and 2D options), ii) graphene capping, and iii) improvements on gap fill (e.g. Electroplating, Electroless plating, selective deposition) to enable higher aspect ratio interconnects. Finally, we will conclude by highlighting the opportunities and demands driven by novel 3D integration schemes, including die/wafer stacking mediated by Thru-Si Vias and Hybrid bonding, as well as monolithic device stacking.

Bio: Mauro J. Kobrinsky received his Ph.D. from the Massachusetts Institute of Technology in 2001. He has been with Intel’s Components Research Division for 19 years; his current position is Director of Interconnects Structures and Architectures. He has contributed to all areas of interconnects research, including process integration, metallization, dielectrics, reliability, interconnects modelling, clock distribution, I/O, photonics, functional materials, 3D integration, and die-package interactions. He holds over 35 patents, and has more than 35 papers and conference presentations. Dr. Kobrinsky has served as a member of the Technical Advisory Board for the Interconnects and Packaging Science area of the Global Research Consortium (GRC), and as a member of the ITRS Interconnect roadmap section.

Abstract: Modern IT technologies has been thriving owing to semiconductor technology progress following Moore’s Law which allows continuous improvements in key aspects of semiconductor chips such as power, performance, area, and cost. DRAM and Flash technologies have evolved successfully overcoming the apparently invincible technical barriers and been the key players in the semiconductor memory market. However, technical barriers are growing larger and larger and it is not easy to respond to all the requirements from various applications of IT era. There are growing concerns about whether such successful evolution will continue. On the other hand, there has been efforts to overcome the difficulties and limits of incumbent memories by developing new type of memories such as MRAM and PRAM. Such new type of memories have promising characteristics such as non-volatility, random access, high speed, and better endurance and attracted strong attention from early 2000s. Even though they have succeeded in starting mass production, they have been staying at niche market so far. In this presentation, challenges in technology scaling of memories such as DRAM, Flash, MRAM, and PRAM and approaches to overcome the technical barriers for future success.

Bio: Gwan-Hyeob Koh is currently a VP at Samsung Electronics and working on the development of STT-MRAM and PRAM. He joined Samsung Electronics in 1997 and was engaged in the development of 1Gb and 4Gb DRAM. Since 2002, he has been working on the development of next generation new memories including MRAM and PRAM. He was involved in the PRAM development from R&D to mass production stage, where his major work was related to process integration, memory device reliability, and yield enhancement. He has been working on the development of STT-MRAM since 2011. He received Ph.D. degree in physics from Seoul National University, Seoul, Korea in 1996. He authored or coauthored more than 60 papers in technical journals and international conferences. He has served as an editor of “IEEE Transactions on Electron Devices” form 2013 to 2018, a subcommittee member of the international conference on “Solid State Devices and Materials (SSDM)” from 2009 to 2015, “International Memory Workshop(IMW)” from 2015 to 2019, and “International Electron Device Meeting(IEDM) “ from 2016 to 2017.

Abstract: Lead-free HfO2 or ZrO2 based CMOS compatible ferroelectric layers even below 10 nm film thickness enable scalable devices like high aspect ratio ferroelectric capacitors (FeCap) and field-effect transistors (FeFET) in 2x nm technology nodes. This short course will cover these non-volatile memory array building blocks but also further applications like ferroelectric tunnel junctions, negative capacitance FETs (NCFET), neuromorphic, piezo, and pyro electric devices are discussed. Ferroelectric properties are caused by a polar orthorhombic structure in polycrystalline films with a grain size of typically 20-30 nm. Transmission electron and piezo force microscopy studies are revealing single grain domain switching kinetics in the pristine case leading to larger (> 100 nm) domains after field cycling. By placing a doped HfO2 layer with a small number of grains within the gate-stack of a nanoscale FeFET structure having a channel length of 30 nm, accumulative switching can be exploited to mimic the integrate-and-fire activity of biological neurons, which, together with FeFET-based synapses, might allow for building fundamental computing blocks of brain-inspired neural networks.

Bio: Uwe Schroeder is Deputy Scientific Director at NaMLab, Dresden since joining in 2009. The main research topics are material properties of ferroelectric hafnium oxide and the integration of the material into future devices. He is mainly involved in process integration, device characterization, and reliability enhancement. Before he worked at Infineon/Qimonda’s DRAM Development Center in Fishkill, New York and Dresden, Germany since 1997. Here, he developed high k dielectrics for their integration into DRAM capacitors. During this time, the so far unknown ferroelectric properties of doped HfO2 based dielectrics were found in 2007. He received his Ph.D. degree from University of Bonn, Germany including a research visit at UC California, Berkeley and worked at University of Chicago as a post-doctoral researcher. He is (co-) author of more than 400 papers and conference contributions and more than 30 patents, including more than 90 peer-reviewed publications, 50 invited presentations on ferroelectric HfO2 material properties and based devices. He (co-) edited a book on ferroelectric HfO2 and serves on the editorial board of IEEE Electron Devices Letters. Uwe Schroeder received the FMA International Award for Ferroelectric Materials and Their Applications in 2019.

Abstract: This short course presentation will cover the history of EUV lithography, basic imaging theory applied specifically to EUV lithography, the technology’s present status – its adoption in the production of 7- and 5-nm generations of logic integrated circuits; and how it can be extended to enable the manufacture of 3-nm logic node and beyond and to future-generation DRAMs.

Bio: Anthony Yen is Vice President and Head of Technology Development Centers, ASML. He joined the company in 2017 with more than thirty years of experience in the field of nanolithography. Dr. Yen received his BSEE degree from Purdue University and his S.M.E.E., Ph.D., and M.B.A. degrees from MIT. From 1991 to 1997, he was at Texas Instruments working on resolution enhancing techniques and an early investigator of optical proximity effects and their correction. From 1997 to 2003, he was with TSMC where he first led the development of its lithography processes, enabling TSMC to be the first company to adopt 193-nm lithography in the manufacturing of 0.13µm logic integrated circuits, and then co-led infrastructure development for next-generation-lithography technologies on assignment at SEMATECH. For three years at Cymer (now part of ASML) he was Senior Vice President responsible for marketing, he returned to TSMC in 2006. As head of Nanopatterning Technology Infrastructure Division, he led the development of EUV lithography, including its mask technology, for high-volume manufacturing which began at the 7 nm node in 2019. Dr. Yen has over 130 US patents and 100 publications. He is a Fellow of the IEEE and SPIE, and a recipient of the Outstanding Electrical and Computer Engineer Award from Purdue University.

Abstract: Through-Silicon-Via (TSV) free monolithic three dimensional integrated circuits (3D-IC) technologies have the advantages of (1) cost-effective manufacturing (2) compact chip small area, (3) low parasitic load for vertical signal transmissions, and (4) highly heterogeneous integration capability, including logic, memory, and sensors. The difficulties in fabricating TSV-free monolithic 3D-IC involve the 3D hetero-integration process using stackable MOSFETs and memories based on low thermal-budget technology. In this short course, major TSV-free monolithic 3DIC technologies will be reviewed including 3D mono-Si/Ge MOSFETs, 3D laser crystallized poly-Si/Ge transistors, 3D carbon nanotube transistors, etc. This short course also will give a view of all the key enablers to develop stackable Si CMOS with low thermal budget technologies, include stackable channel formation, gate stack, junction activation, etc. Finally, monolithic 3D neuromorphic computing technology also will be discussed.

Bio: Chang-Hong Shen received his Ph.D. in physics at National Tsing-Hua University, Taiwan, in 2006. From 2007, he joined Mosel Vitelic in Taiwan. From 2009, he jointed National Nano Device Laboratories as associate researcher. Currently he is a Researcher Fellow in Taiwan Semiconductor Research Institute (TSRI) (former NDL). His current research focuses on developing Si photovoltaic/photonic/electronic devices, low cost monolithic 3D circuits. He has published over ten monolithic 3DIC papers at IEDM with two papers selected as IEDM publicity materials. He also was a sub-committee member in the CDI and ALT sections of IEDM 2018 and 2019 respectively.

Abstract: Amorphous oxide semiconductors have recently found commercial success in the form of thin film transistors for display applications. This short course will start with an overview of the fundamental advantage of amorphous oxide semiconductors as channel materials for low temperature processed transistors over their covalent semiconductor counterparts. We will identify the potential avenues for aggressive scaling of the oxide transistors and explore disruptive electronics, for example, three dimensional monolithic integrated circuits, enabled by oxide electronics embedded in the back-end-of-line (BEOL). We will evaluate the critical electrical characteristics, such as carrier transport, electrostatics, stability, endurance, extrinsic resistance associated with today’s oxide semiconductor transistors fabricated at low temperatures, and their future improvement strategies. Finally, we will conclude with a benchmark study of the current and projected performance of oxide transistors with other semiconductor channel materials for BEOL transistor applications.

Bio: Suman Datta was with the Logic Technology Development group at Intel Corporation, Hillsboro, OR, USA, from 1999 to 2007, where he developed several generations of high-performance logic transistor technologies, including high-k/metal gate, tri-gate, and non-silicon channel CMOS transistors. He was a Professor of Electrical Engineering with Pennsylvania State University at University Park, University Park, PA, USA, from 2007 to 2011. He is currently the Stinson Chair Professor in Electrical Engineering with the University of Notre Dame, Notre Dame, IN, USA. He is the Director of a Multi-University Advanced Microelectronics Research Center, the ASCENT, funded by the Semiconductor Research Corporation and the Defense Advanced Research Projects Agency. He has published over 350 journals and refereed conference papers and holds 180 patents related to advanced semiconductors. He is a Fellow of the IEEE.

Abstract: The global semiconductor industry attempts to add values and extend functionalities within a single chip. Monolithic 3-D integration has emerged as a promising technological solution for high density, high performance, and multi-functional integrated circuits. Layer transfer technology of Ge and III-V semiconductors has attracted a lot of attention since these materials can be processed at low temperature and provide extended opportunity/functionality via heterogeneous material integration. Key challenges are how to manage material qualities of transferred layers, and how to fabricate high performance 3D devices under low-thermal budget process without performance degradation. In this talk, we discuss layer transfer technology for integrating Ge and III-V devices and its applicability to CMOS and photonics platforms for creating monolithic 3-D chip of the future.

Bio: Tatsuro Maeda is Research Manager in National Institute of Industrial Science and Technology (AIST), Ibaraki, Japan. His current research interests include heterogeneous integration of post-silicon devices such as SiGe, Ge, and III-V materials on Si platforms for future monolithic 3D application. He received the Ph.D. degree in material science from Tokyo Institute of Technology in Japan in 1996. In 1996, he joined the Electron Device Division, Electrotechnical Laboratory, Ibaraki, Japan where he has been engaged in the research on fabrication and characterization of ultra-small SOI-MOSFETs, nano-scaled Si-based devices, and single electron transistors for future CMOS components. In 2001, he joined AIST as a senior researcher. Now he belongs to Device Technology Research Institute in AIST. He has authored or co-authored over 100 publications and conference presentations related to nanoelectronics research.