Abstract: Interconnects advancements are critical to enabling Moore’s law. Each technology node demands: (1) pitch scaling at the lower metal layers to enable cell area reduction; (2) increasing number of interconnect layers; and (3) improvements in capacitance, line and via resistance on all layers (performance). In addition, 3D integration trends, including die and wafer stacking, create new challenges and open new opportunities. Future scaling research paths that include device stacking and novel power distribution schemes bring about need for additional interconnect advancements. In parallel, the impact of interconnects on overall part performance generates increased attention and visibility to interconnects. These ongoing trends have made Interconnect research one of the most dynamic and exciting areas in the Semiconductor Industry, abundant with exciting new ideas, challenges and opportunities. In this short course, we will first review the basic geometries, performance needs, and scaling trends of interconnects. We will also highlight a few of the most significant advances in the past 20 years. We will then discuss the most exciting leading options that Industry and Academia are exploring for future technology nodes. For scaling to 20 nm pitch and below, we will cover subtractive interconnects, new material options, and patterning techniques for shorting margin, such as self-alignment techniques and selective deposition. For mid-pitch intermediate layers, we will cover progress on three methods to improve performance: i) barrier/liner thinning (standard and 2D options), ii) graphene capping, and iii) improvements on gap fill (e.g. Electroplating, Electroless plating, selective deposition) to enable higher aspect ratio interconnects. Finally, we will conclude by highlighting the opportunities and demands driven by novel 3D integration schemes, including die/wafer stacking mediated by Thru-Si Vias and Hybrid bonding, as well as monolithic device stacking.
Bio: Mauro J. Kobrinsky received his Ph.D. from the Massachusetts Institute of Technology in 2001. He has been with Intel’s Components Research Division for 19 years; his current position is Director of Interconnects Structures and Architectures. He has contributed to all areas of interconnects research, including process integration, metallization, dielectrics, reliability, interconnects modelling, clock distribution, I/O, photonics, functional materials, 3D integration, and die-package interactions. He holds over 35 patents, and has more than 35 papers and conference presentations. Dr. Kobrinsky has served as a member of the Technical Advisory Board for the Interconnects and Packaging Science area of the Global Research Consortium (GRC), and as a member of the ITRS Interconnect roadmap section.