Abstract: Chiplet architecture has been much discussed and debated, but today we are seeing real world architectural solutions based on chiplets in high volume production and mainstream markets. The benefits of these approaches in enabling lower costs from smaller die combined with modularity to scale performance and configuration will be covered, with examples take from industry products. The costs of splitting and modularizing an SOC into chiplets will be discussed, which include the need to support high bandwidth and low latency communication between the die, overheads of testing and power managing what used to be individual SOC modules as standalone chips, and engineering the package substrate to provide routing and power delivery resources for the complex arrangement. Next will be an exploration of the fascinating optimization landscape these costs and benefits provide for finding the optimal application of chiplet architecture across product lines, both in the near term and looking into the next decade of innovation.
Bio: Samuel Naffziger is a Corporate Fellow at AMD responsible for technical strategy with a focus on power technology development. He has been the lead innovator behind many of AMD’s low power features and chiplet architecture. He has over 31 years of industry experience with a background in microprocessors and circuit design, starting at Hewlett Packard, moving to Intel and then at AMD since 2006. He received the B.S.E.E. from the California Institute of Technology, Pasadena, CA, in 1988 and M.S.E.E. from Stanford University, Stanford, CA, in 1993 and holds over 130 US patents in the field. He has authored dozens of publications and presentations on processors, architecture and power management and is a Fellow of the IEEE.