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Joint Circuits & Technology Short Course

Abstract: Chiplet architecture has been much discussed and debated, but today we are seeing real world architectural solutions based on chiplets in high volume production and mainstream markets. The benefits of these approaches in enabling lower costs from smaller die combined with modularity to scale performance and configuration will be covered, with examples take from industry products. The costs of splitting and modularizing an SOC into chiplets will be discussed, which include the need to support high bandwidth and low latency communication between the die, overheads of testing and power managing what used to be individual SOC modules as standalone chips, and engineering the package substrate to provide routing and power delivery resources for the complex arrangement. Next will be an exploration of the fascinating optimization landscape these costs and benefits provide for finding the optimal application of chiplet architecture across product lines, both in the near term and looking into the next decade of innovation.

Bio: Samuel Naffziger is a Corporate Fellow at AMD responsible for technical strategy with a focus on power technology development. He has been the lead innovator behind many of AMD’s low power features and chiplet architecture. He has over 31 years of industry experience with a background in microprocessors and circuit design, starting at Hewlett Packard, moving to Intel and then at AMD since 2006. He received the B.S.E.E. from the California Institute of Technology, Pasadena, CA, in 1988 and M.S.E.E. from Stanford University, Stanford, CA, in 1993 and holds over 130 US patents in the field. He has authored dozens of publications and presentations on processors, architecture and power management and is a Fellow of the IEEE.

Abstract: High-density 2.5D and 3D integration technology will be used to realize “3D-SOC” heterogeneous systems to enable more complex, higher functionality, and higher performance systems than through traditional device scaling alone. This requires high bandwidth, low latency, and low energy chiplet-to-chiplet interconnect. With 3D integration being a very active field in the past decade, many technology directions have been proposed with a plethora of names and acronyms spawned to distinguish them apart. Unfortunately, this has created user confusion when comparing and selecting technologies for system applications. We propose a hierarchical view of the interconnect fabric, which we define as a 3D landscape, that extends from the die to the 3D interconnect level to span eight orders of magnitude in interconnect density. We will cover current technologies, as well as emerging ones in development, used to realize 2.5D systems, 3D stacked ICs, and 3D wafer-to-wafer stacking for 3D-SOCs. Technology elements such as Si interposers, through-silicon vias, solder microbumping, and hybrid wafer-to-wafer or die-to-wafer bonding will be discussed in detail.

Bio: Eric Beyne obtained a degree in electrical engineering in 1983 and the Ph.D. degree in applied sciences in 1990, both from the Katholieke Universiteit Leuven, Belgium. Since 1986, he has been with imec in Leuven, Belgium, where he has worked on advanced packaging and 3D interconnect technologies. Dr. Beyne is currently imec Fellow, VP R&D, and Program Director of imec’s 3D System Integration program.

Abstract: With transistor scaling reaching both physical and economic barriers, transistor performance and cost have been increasingly lagging behind the historical Moore’s Law trajectory. However, demand for silicon remains incessant with the growth of internet traffic, artificial intelligence, autonomous driving, and big data. One solution to meet this demand is to integrate multiple dies into a package that is a so-called backend-based chiplet package. Chiplet packages are designed either heterogeneously or homogeneously with integrated devices. Over the years, electronic assembly houses have developed a plethora of chiplet technologies such as Flip Chip Multi Chip Module (FCMCM), 2.1D, 2.5D, 3D, Fan-Out MCM (FOMCM), and Fan-Out Embedded Bridge (FOEB). In this presentation, we review the advantages and disadvantages of chiplet-based designs, discuss their challenges and solutions, and offer chiplet trends.

Bio: C. Key Chung received his B.Sc. degree from Nanyang Technological University, Singapore, and Ph.D. degree from National Taiwan University, Taipei, both in materials science and engineering. He is currently the Senior Director of Advanced Package R&D at SPIL responsible for advanced chiplet packaging pathfinding, development, and initial ramp-up across different business units. Dr. Chung and his team have successfully won several advanced packaging businesses in five years including ultra-thin FO-PoP, FOMCM, FOEB, 2.1D, 2.5D, and 3DIC packaging. He has been involved in electronic assembly for 26 years, focusing on packaging, substrate and assembly material technology development, and having also worked at HP and Intel. He is a recognized expert in solder joint interconnection and a standing reviewer for the Journal of Alloys and Compounds from which he received the outstanding reviewer award. He has authored over 20 patents, over 30 journal and conference papers, and multiple invited talks at international conferences.

Abstract: The interest in AI has exploded over the past few years and the use of AI in applications is poised to increase dramatically for many years. However, AI already demands very large amounts of compute, memory, and bandwidth; how to deliver these levels is becoming a pervasive challenge in computing system design. This explosive growth has provided a huge impetus to accelerate AI workloads by employing a mix of diverse components, including CPUs, GPUs, specialized accelerators, and memories. The requirement of high bandwidth interconnectivity between different components has been a major driver for heterogeneous integration. In addition, the diminishing node-to-node returns from scaling have propelled heterogeneous integration to the forefront of technology focus. This raises several questions. How does the current state-of-the-art in heterogeneous integration meet the ever-growing demands of AI? What novel integration schemes are needed to deliver continued gains in system performance? How can emerging memories and analog technologies, which show promise for accelerating AI workloads, be effectively integrated with conventional technologies? Finally, what is the path forward to deploy heterogeneous integration as a pervasive technology in this arena? We will examine both the architecture requirements for AI as well as the heterogeneous integration methods needed to enable an upward trajectory for system performance.

Bio:
Arvind Kumar is a manager of AI Hardware Technologies at the IBM T.J. Watson Research Center. His research focuses on the requirements of AI systems and the heterogeneous integration innovations to accelerate them. He has presented a number of invited talks and been a panelist in this area. In addition, he has chaired and organized a number of future computing events, including the 2017 IEEE Rebooting Computing Conference. Prior to concentrating on AI, he worked extensively on device design, characterization, and simulation for several IBM SOI technologies. Dr. Kumar holds S.B., S.M., and Ph.D. degrees in electrical engineering and computer science, all from the Massachusetts Institute of Technology.

Mukta Ghate Farooq is a metallurgist and materials scientist with expertise in heterogeneous integration, CMOS BEOL, lead-free alloys, and chip-package interaction. She is currently the 3D Integration Leader for the Artificial Intelligence Center (AIC) at IBM Research. Mukta was the IBM technology leader who delivered the semiconductor industry’s first high-volume 3D logic wafer in 2013. Mukta is an IEEE Fellow, an IEEE EDS Distinguished Lecturer, and a Distinguished Alumna of IIT-Bombay. She has 216 granted US patents and is an IBM Lifetime Master Inventor and an IBM Academy of Technology member. She received her B.S. from the Indian Institute of Technology, Bombay, M.S. from Northwestern University, Evanston, IL, and Ph.D. from Rensselaer Polytechnic Institute, Troy, NY.

Abstract: System-in-Package (SiP), heterogeneous integration, and 3D interconnect are frequently coined as technologies that will disrupt Moore’s Law. Yet in the field of MEMS and sensors, these technologies have already been essential to successful product development for several years. Most MEMS sensors employ heterogeneous integration to co-package at least one die with dedicated micromachined technology and a standard IC that translates the electrical signals from the mechanical sensing element to a user-friendly signal. Here, 3D integration overcomes form factor challenges limited by conventional 2D interconnects. For example, caps or cans of various materials are used in environmental sensors for both protection and sensing ports while substrate passive components are commonly used in microphones. We will present state-of-the-art 3D integration techniques applied to MEMS and sensor packaging and offer an outlook on the convergence of the MEMS roadmap with advanced packaging solutions. We will cover the chiplet SiP approach for sensors; mechanical chiplets such as caps, cans, filters, and other mechanical parts that sense and transmit physical signals; novel usage of existing materials in a sensor assembly; and examples and future trends where sensors drive the package technology.

Bio: Marco Del Sarto received his M.D. in 2000 from the University of Pisa, Italy. His thesis work was on Lab-On-Chip developed at STMicroelectronics. He joined STMicroelectronics in 2001 as a MEMS designer in the area of testing, modeling, and simulation. From 2003 to 2006, he led the technical program management to industrialize the first MEMS accelerometers. From 2006 to 2016, he served a broad range of roles in the MEMS product quality department from customer quality assurance to department management. He concurrently managed the validation and characterization team working on MEMS sensors. Since 2016, he has been driving the package design R&D team for MEMS sensors.

Abstract: More now than ever, conventional single-die package systems are facing both performance and cost challenges with continued CMOS scaling. As such, System-in-Package solutions, where multiple chiplets are integrated by various 2.5D/3D substrate technologies, have become lucrative alternatives. To be economically viable, they require carefully co-optimizing system demand and package technology as well as the interconnects that enable communication between the chiplets. From a system perspective, the interface circuits need to be transparent to minimize power, area, and latency overhead. Here, we will briefly introduce prominent 2.5D/3D package technologies and outline opportunities and challenges presented by these technologies. We will explore circuit design and test considerations for these ultrashort-haul inter-chiplet links, covering topics such as clock schemes and synchronization, low-power design strategies, interconnect routing, and design for testability. We will also discuss recent design examples demonstrating high aggregate data bandwidth at high energy efficiency.

Bio: Kenny C. H. Hsieh received his B.S.E.E. degree from National Cheng Kung University, Tainan, Taiwan, and M.S.E.E. degree from National Chiao Tung University, Hsinchu, Taiwan, in 1985 and 1989 respectively. He designed SRAM and DRAM circuits at Winbond and Etron for 6 years prior to spending several years in PLL and Gm-C filter research at the University of California, Irvine. In 1997 to 20012, he designed high-speed SerDes at Ohm Technology, LSI/Avago, and Xilinx in California. Mr. Hsieh joined TSMC in 2012 where he is currently a Deputy Director leading a mixed-signal design group. His current research interests include equalization theory for digital communication and design/technology co-optimization of advanced CMOS technologies.

Abstract: 2.5D and 3D integrated circuits bring together complex logic and memory components, manufactured as multiple dies or chiplets, from the circuit board on to the same package. Modern 3DIC packaging technology is evolving rapidly and the 3DIC tools need to be versatile enough to handle a range of styles, across the space of 2.5D and 3D, including elements such as silicon interposers, silicon bridges, organic substrates, and their integrated combinations. The tools for design and verification of these chiplet/package combinations need to have high enough capacity to enable efficient co-optimization of the chiplets and the package. Design implementation tools need to enable the design of interconnect routes, microbumps on the chiplets, C4 bumps on the package, and through-silicon vias (TSVs) to be laid out with flexible layout styles to meet demanding electrical requirements including inductance effects. Signoff tools need to verify the power integrity, signal integrity and thermal integrity of the 3D system, with high enough accuracy to ensure the functioning and the performance, while enabling fast enough early feedback for optimization of the package design. DFT poses challenges because there is limited access to internal signals on the package and tools need to interoperate with new standards for addressing this. Special layout checks are needed to ensure proper connectivity of the chiplets via the package layout and to detect issues early. Above all, the 2.5D/3D IC tools should enable designers to explore the design space and efficiently converge on decisions to optimize the performance and power with minimal cost.

Bio: Rajesh Gupta is a Senior Director of Methodology at Synopsys, working on 3D IC tools and solutions. Previously, he worked at Samsung where he was responsible for CAD and design methodology for Samsung’s premium mobile processor designs. Before that he has held positions at Intel, on methodology development for the Atom processor designs, and at IBM, on EDA tool development for IBM’s very first Gigahertz Processor. Dr. Gupta has a B.Tech. from the Indian Institute of Technology, Madras and a Ph.D. from the University of Southern California, Los Angeles.

Abstract: 2.5D/3D heterogeneous system integration is rapidly evolving to be the most promising solution to extend the celebrated historical Moore’s Law in the semiconductor industry. It has already been successfully deployed in various applications including high-performance computing, high-end graphics, and mobile computing. In this talk, we introduce state-of-the-art 2.5D/3D integration techniques such as chip partitioning, die-to-die interface, through-silicon-via (TSV) signaling, power delivery, and thermal considerations. Using 8-Hi/12-Hi 3D-stacked HBM2E as a practical example, we will present generic design strategies and considerations for 2.5D and 3D stacked IC ranging from power-efficient design techniques and performance optimization methods to stacked-die bit-cell reliability and design for testability.

Bio: Ki Chul Chun is a Principal Engineer and a Project Lead of HBM (High Bandwidth DRAM) chip design at Samsung Electronics. He received the B.S.E.E. degree from Yonsei University, Seoul, Korea, in 1998, the M.S.E.E. degree from KAIST, Daejeon, Korea, in 2000, and the Ph.D.E.E. degree from the University of Minnesota, Minneapolis in 2012. In 2000, he joined the Memory Division, Samsung Electronics, Hwasung, Korea, where he has been involved in low-power DRAM circuit design. After his Ph.D., he rejoined Samsung Electronics in 2012, where he has worked on low-power DRAM and HBM chip design. Dr. Chun received the ISLPED Low Power Design Contest Awards in 2009 with an embedded DRAM design and in 2012 with an embedded FLASH design. His research interests include 3D-DRAM circuit design and technology, low-power and high-speed DRAM design, and universal memory design such as STT-MRAM in scaled technologies.