Technologies and Circuits for Edge Intelligence

Abstract: Edge Intelligence (EI) is the ability to analyze data locally at the point where the data is being collected, formulate a decision based on that analysis and execute that decision autonomously without human interaction. It is core to the original definition of IoT devices but was lost due to technology limitations at the time IoT devices were first created. The communication centric approach where the IoT device relies on communication of the raw data to the Cloud, where the data is analyzed and decisions are formulated, was the result of these limitations.

Communication bandwidth, energy inefficiency of data communication, latency and security have become the key limiters preventing IoT to become the engine of growth for the semiconductor industry. EI is about to change this. In this forum these limitations and how EI will address them and what is needed for EI to become a reality will be addressed. At the center of EI is the small system AI engine.

Talk FF.1 will introduce a path for a processing engine that is not based on a von Neumann architecture, but on In Memory Computing and is capable of a compute performance of 1 TOPS while consuming only 1 mW of power, enabling the reliance on scavenged energy and thus creating energy autonomy. And how a new technology platform will enable the building of such an engine. In the other talks the challenges of EI sensors (smart sensors, FF.7), AI engines (FF.8), energy autonomy (FF.4), communication (FF.6) and security (FF.9) will be covered. Foundational technology talks are FF.3 and FF.5. In talk FF.2 the impact of all this on the world we live in will be discussed.

We will have a live session on June 17 at 6:00am PDT that includes a panel of forum speakers plus Q&A that will be moderated by Ali Keshavarzi of Stanford University.

Abstract: Edge Intelligence (EI) enables smart devices to sense, decide with, act on, and send information at the point of raw data collection rather than relying on the cloud. This archetype of Artificial Intelligence (AI) in small efficient systems is a key enabler for a wide range of applications, projected to reach a trillion Internet of Things (IoT) devices. Turning sensed data into actionable information locally allows for a careful balance of energy-efficient computing and communication demands, at the intersection of Moore’s Law and the Shannon-Hartley Theorem, resulting in minimized system energy consumption. Enabling devices to operate autonomously and sustainably in challenging and energy-constrained environments at a competitive SWaP-C metrics presents extraordinary technical challenges. Today, we will explore this interdisciplinary research field covering all scales – materials, devices, circuits, design, architectures, and implementations – to expand the vision of EI, defining the requirements of an engine for small-system AI and exploring the means to achieve them.

Bio: Ali Keshavarzi has been at the forefront of semiconductor technology innovation with a track record of successfully delivering critical technologies, devices, circuits, chips and modules for over 27 years. He has been at the leading edge of R&D in CMOS technology scaling, planar and FinFET devices, circuits and design for low-power, low-voltage electronics, and high-performance computing, low-power and programmable SoCs, wide IO and high bandwidth memories, differentiated technology solutions by embedded non-volatile memory (eNVM), advanced multi-chip fan-out, Systems embedded in Package (SeP), and 2.5D packaging. Dr. Keshavarzi was the Vice President of R&D and a technical Fellow at Cypress Semiconductor. He has had various senior R&D roles at Intel, TSMC, and GlobalFoundries. Dr. Keshavarzi is the founder of Leading Edge Research (LER) company. Dr. Keshavarzi is an adjunct professor at Stanford University and was a visiting research scholar at UC Berkeley engaged in various research vectors in the field of low-power electronics and driving the vision of Edge Intelligence (EI) that enables smart devices to sense, decide with, act on, and send information at the point of raw data collection rather than relying on the cloud. He is also serving as an advisor to DARPA. Dr. Keshavarzi has over 65 granted patents and over 55 peer-reviewed papers.

Abstract: Global trend toward Edge Processing is not all about technology, not all about how many devices can we put on every person on the earth, and not at all about selling more technology. At the heart of this revolution is a paradigm shift that will propel us to build a responsible society that is more energy efficient, more productive, honoring individual safety and privacy. In this talk, we will discuss why it makes sense to embrace Edge Processing revolution, what technology companies like us are doing to drive its growth, challenges and opportunities ahead of all us.

Bio: Gowrishankar (Gowri) Chindalore is Head of Technology and Business Strategy for Industrial, IoT & Edge Processing with revenues of more than $1.5B at NXP Semiconductors, Inc. His team is responsible for studying global trends, identify growth opportunities, developing product strategy, competency gap assessments, and merger & acquisitions evaluations. Gowri has over 20 years of experience in the semiconductor field, spending his first fifteen years in R&D of innovative flash memory, radar and SoC technologies. He is the co-inventor of 75 issued patents and co-authored over 30 publications in the areas quantum mechanical effects, embedded flash memories, SoC integration and quality. Gowri obtained his Ph.D. in microelectronics from The University of Texas at Austin.

Abstract: Edge computing and intelligence has gained momentum recently, made possible partially by novel in-package heterogeneous system integration. An overview on package-level heterogeneous integration platforms are discussed with focus on current products using state-of-the-art technologies. Close proximity at all levels, including chip-to-chip, and horizontal/vertical interconnection density is the underlying enabler for realizing edge device high performance computing using in-package multi-chip system integration technologies. Technology challenges and outlooks with future prospective are discussed as a summary.

Bio: Chih Hang Tung is Deputy Director of Exploratory 3D Program in TSMC R&D. He has worked in the Taiwan and Singapore semiconductor industry for over 30 years, covering areas including FEOL HKMG, silicide, to BEOL Cu low-k, and to far-back-end 3DIC and advanced packaging. Chih Hang has his M.S. degree from Illinois Institute of Technology (Chicago), has authored/co-authored for more than 250 peer reviewed papers, 30+ US patents, and a book “ULSI Semiconductor Technology Atlas” (Wiley 2003). He served as IEEE IPFA Chair in 2008, EDS Distinguished Lecturer (2007-2010), senior member since 2002, and received the IEEE EDS Paul Rappaport Award in 2008. He joined TSMC in 2008 and currently works in 3DIC and system integration.

Abstract: Self powered systems on chip harvest energy from their environment and remove the need for batteries, which is essential for allowing the Internet of Things to scale toward a trillion or more edge devices. This talk describes how self powered systems operate to meet application needs. Using an example industrial application, the application needs define requirements for the system on chip that support the harvesting context, the network needs, and computation at the edge. An example self powered system on chip shows how these capabilities are integrated into a device that intelligently operates without batteries.

Bio: Benton H. Calhoun received the M.S. degree and Ph.D. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, MA, in 2002 and 2006, respectively. In 2006, he joined the faculty at the University of Virginia in the Electrical and Computer Engineering Department, where he is now a Professor. His research has emphasized energy efficient and sub-threshold integrated circuit design for self-powered, batteryless wireless sensing systems. Dr. Calhoun has over 200 peer reviewed publications and 22 issued US patents. He co-founded and is co-CTO at Everactive, Inc., which is selling self-powered, energy harvesting wireless sensing solutions in the industrial IoT market. He is a senior member of the IEEE.

Abstract: The advent of modern smart phones transformed our lives and our daily routines profoundly. This has become even more evident during the current Covid-19 pandemic; it has been reported that the usage of edge devices has substantially increased. Mobile phones are no longer simple devices. They are nowadays vital to connect us to the outside world.  CMOS technology has been crucial to advance the capabilities of these devices, and CMOS scaling has been essential to make these devices more affordable, faster, and more and more energy-efficient.  Indeed, CMOS technology has been a remarkable success story of disruptive innovations spanning the fields of material sciences, device physics, and circuit design.  During the last few years, the evolution from planar CMOS devices to FinFET has enabled a new era of scaled CMOS technologies. However, it cannot stop here. Disruptive innovations beyond these architectures are now required to maintain performance and power scaling for next-generation energy-efficient edge computing.  In this talk, we would like to share our view of the evolving CMOS technology roadmap that needs to be followed to further advance the edge technology toward edge-computing.

Bio: Myung-Hee Na is a semiconductor technologist and currently work at imec as the Vice President of Technology Solutions and Enablement. She is currently responsible for CMOS and AI hardware technology research for new semiconductor era. Dr. Na received a Ph.D. in hhysics and started her career at IBM in 2001 where she held various technical, managerial and executive roles until early 2019. At IBM, she successfully led Research and Development for multiple generations of semiconductor technologies, including high-K metal gate, FinFET, and Nanosheet development. Moreover, she has co-authored numerous research papers and holds several U.S. and international patents.

Abstract: With standards such as 6TiSCH, IEEE802.15.4 TSCH and WirelessHART, the IoT has been going industrial for a number of years. Tens of thousands of such low-power wireless networks have been deployed in application domains as varied as Smart Factory, Smart Building, Smart Home and Environmental. Off-the-shelf products such as Analog Devices’ SmartMesh IP offer >99.999% end-to-end reliability and over a decade of battery lifetime. Innovation in this domain also comes from vibrant open-source communities. We will first go through an overview of the key technology of the IIoT, and talk about what standards and products are available today. We will show numerous examples of where they are being used, all drawn from years of experience in real-world deployments. We will finish by discussing the research challenges ahead, both on dependable and technology-agile networking, and on crystal-free “Smart Dust” type architectures.

Bio: Thomas Watteyne is an insatiable enthusiast of low-power wireless mesh technologies. He is Senior Networking Design Engineer at Analog Devices, in the Dust Networks product group, the undisputed leader in supplying low power wireless mesh networks for demanding industrial process automation applications. He also holds a Research Director position at Inria in Paris, in the EVA research team, where he leads a team that designs, models and builds networking solutions based on a variety of Internet-of-Things (IoT) standards. Since 2013, he co-chairs the IETF 6TiSCH working group, which standardizes how to use IEEE802.15.4e TSCH in IPv6-enabled mesh networks. Prior to that, Thomas was a post-doctoral research lead in Prof. Kristofer Pister’s team at the University of California, Berkeley. He founded and co-leads Berkeley’s OpenWSN project, an open-source initiative to promote the use of fully standards-based protocol stacks for the IoT. Between 2005 and 2008, he was a research engineer at France Telecom, Orange Labs. He holds a Ph.D. in computer science (2008), an M.Sc. in Networking (2005) and an M.Eng. in telecommunications (2005) from INSA Lyon, France. He is an IEEE Senior Member.

Abstract: Today , the performance of image sensors exceeds the capabilities of the human eye and can provide more immersive experiences as a result. In addition, the image sensors for sensing can digitize various other kinds of information than typical 2 dimensional images where applications such as authentication, recognition, autonomous machine control, and wireless products further process this useful and efficient information. These latest sensors enhance the quality of services and the evolution of image sensing systems grow into a broader information conversion tool. In this talk, the requirements for smart vision sensors in high-speed and event-based processing systems for industrial automation and always-on sensing applications will be discussed. The performance requirements for these new application will be demonstrated. Finally, our vision of how the upcoming combination of Smart Vision Sensor and Artificial Intelligence technologies will profoundly influence our lifestyle, will be introduced.

Bio: Hayato Wakabayashi is a Deputy General Manager of the Research dDvision at Sony Semiconductor Solutions Corporation. He received a B S and M Sc in engineering from Osaka University, Japan respectively and Ph. D. from Tohoku University, Japan. He served on the technical program committee of the Symposium on VLSI Circuits from 2014 to 2017 and has been engaged in a member of the technical program committee of International Solid-State Circuits Conference since 2017. He received the Walter Kosonocky Award for the paper on back-illuminated CMOS image sensor in 2011. He is currently working on the research and development of future imaging and sensing devices, circuits and systems.

Abstract: As edge devices are becoming ubiquitous, it is increasingly important for them to be equipped with efficient hardware engines for intelligence.  Such engines allow devices to respond to only meaning events, thereby greatly reducing power consumption and data transfer. In addition, having inference engines on Edge devices allows for extracted features to be transferred to the cloud instead of raw data, providing a greater degree of security and privacy. In this presentation, we discuss possible approaches for making efficient neural engines for Edge devices. Since such inference engines are typically “always on”, low power consumption is critical. We discuss possible on-chip memory hierarchies for making all-on-chip wright storage more energy efficient as well as in-memory computation.  We complete our presentation with a case study of a voice activity detection system which consumes < 200nW and measures less than 10 millimeters on a side.

Bio: David Blaauw received his B.S. in physics and computer science from Duke University in 1986 and his Ph.D. in computer science from the University of Illinois at Urbana-Champaign in 1991. Until August 2001, he worked for Motorola, Inc. in Austin, TX, where he was the manager of the High Performance Design Technology group and won the Motorola Innovation award. Since August 2001, he has been on the faculty of the University of Michigan, where he is the Kensall D. Wise Collegiate Professor of EECS. He has published over 600 papers, has received numerous best paper awards and holds 65 patents. He has performed extensive research in ultra-low-power computing using subthreshold operation and analog circuits for millimeter sensor systems, which was selected by the MIT Technology Review as one of the year’s most significant innovations. For high-end servers, his research group introduced near-threshold computing, which has become common in semiconductor design. Most recently, he has pursued research in cognitive computing using analog, in-memory neural-networks for edge-devices and genomics acceleration for precision health. He was the ISLP general chair, the technical program chair for DAC, and serves on the ISSCC technical program committee. He is an IEEE Fellow and received the 2016 SIA-SRC faculty award for lifetime research contributions to the U.S. semiconductor industry.

Abstract: As IoT deployments expand, security lags infamously behind. In this talk I will provide an overview of the latest developments around IoT security, focusing on low-end IoT devices using Arm Cortex M microcontrollers. Particular attention is paid to the interworking between hardware security technologies, such as TrustZone for v8-M, and emerging IoT security standards utilizing these hardware features. The talk will conclude with an outlook of how the Platform Security Architecture (PSA) can help companies to take the next steps in improving security of their IoT devices.

Bio: Hannes Tschofenig is currently with Arm. Prior employers include the European Data Protection Supervisor, Nokia Networks, and Siemens. His work focused on developing global standards to make the Internet work better. He has been active in the Internet Engineering Task Force (IETF) for the past 18 years, contributing more than 80 RFCs on security, privacy, IoT, and emergency services. Hannes co-chaired various IETF groups, including the “Web Authorization Protocol” (OAuth) working group and the “Authentication and Authorization for Constrained Environments (ace)” working group. From 2010 to 2014, Hannes was a member of the Internet Architecture Board (IAB), a committee of the IETF. He was also vice-chair of the FIDO Alliance Privacy and Public Policy Working Group. The FIDO (Fast IDentity Online) Alliance aims to change the nature of authentication on the Web by developing specifications that reduce the reliance on passwords. Recently, Hannes has been active in OMA SpecWorks, an organization working on the IoT device life-cycle management protocol LwM2M. Besides being a board member of OMA SpecWorks he also chairs the Device Management & Service Enablement working group.