Abstract: The last twenty years has seen an incredible explosion of adaptive circuit and system techniques, especially in the area of high-performance microprocessor design. While general purpose microprocessors continue to be essential components of any computing platform, their programmability and inherent flexibility cause them to have less performance, and less power efficiency, as compared to more structured designs such as GPUs, FPGAs, and ASICs. This deficiency has driven a significant amount of design effort to provide adaptive techniques in hardware to maximize the performance delivered, significantly improve power efficiency, and dramatically increase battery life. This talk will summarize the last twenty years of innovation, including topics such has voltage & frequency scaling, power gating, droop mitigation techniques, methods to mitigate process and environmental variation, as well as design and system-level mechanisms to enable reliability-aware performance optimizations. The talk will conclude by prognosticating what techniques we may see in future products.
Bio: Thomas Burd received the B.S, M.S, and Ph.D. degrees in electrical engineering and computer science from the University of California at Berkeley, in 1992, 1994, and 2001, respectively. He was a Consultant with multiple startups in Silicon Valley. In 2005, he joined Advanced Micro Devices, Santa Clara, CA, USA, where he has worked on multiple generations of high-performance x86 cores (including the Bulldozer and Zen families of cores) in physical design architecture, design for reliability, power delivery, and analysis methodology. He is currently a Senior Fellow Design Engineer and Physical Design Architect for the next-generation Zen core. He has authored over 25 conference and journal publications, in addition to the book Energy Efficient Microprocessor Design. He is an inventor of five U.S. patents. Dr. Burd has been serving on the ISSCC Technical Program Committee since 2017, where he is current the Digital Architectures and Systems Subcommittee Chair. He served on the Technical Program Committee for the Symposium on Very Large Scale Integration Circuits from 2012 to 2015, ICCAD from 2003 to 2005, and Hot Chips in 1996. He was a recipient of the 2001 ISSCC Lewis Winner Award for the Best Conference Paper and the 1998 Analog Devices Outstanding Student Award for recognition of excellence in IC design. He is a Senior Member of the IEEE.