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Trends and Advancements in Circuit Design

Abstract: With ever increasing appetites for higher performance, higher bandwidth, and more energy efficient computing driven by applications such as Machine Learning and Autonomous Driving, circuits need to continue to advance to satisfy the evolving and growing demands.  This short course seeks to survey various key areas in circuit design by observing their historical and recent trends, state of the art developments, and their future directions.  Topics span from analog and digital designs to communications, and cover data converters, sensors, frequency generators, wireline & wireless communications, adaptive circuits, and emerging memory designs.

Abstract: With the increasing demand of integrating voltage regulators completely on silicon, switched-capacitor (SC) converters that consist of only capacitors and switches are gaining popularity as substitutes or alternatives for inductor-based DC-DC converters. Step-up SC converters are also known as charge pumps, and handheld applications need mainly step-down charge pumps. This short course starts with charge balance law, followed by topological consideration, integrated circuit design technique and performance analysis. Step-up and step-down converters, 2-phase and multi-phase topologies and interleaving schemes for ripple reduction will be discussed.

Bio: Wing-Hung Ki received his B.Sc. degree (1984) from the University of California, San Diego, the M.Sc. degree (1985) from the California Institute of Technology, Pasadena, and the Ph.D. degree (1995) from the University of California, Los Angeles, all in electrical engineering. He first joined Micro Linear Corporation, San Jose, from 1992 to 1995, working on the design of power converter controllers. He then joined the Hong Kong University of Science and Technology in 1995. He is now a professor of the Department of Electronic and Computer Engineering. His research interests are integrated circuit techniques for power management circuits such as switched-inductor converters, switched-capacitor converters, low dropout regulators, wireless charging and implantable biomedical devices, and fundamental research in circuit analysis and design.

Abstract: The noise-shaping SAR technique, introduced in 2012, combines the efficiency of the SAR technique with noise-shaping. Noise-shaping extends the efficiency of SAR to higher resolution. Indeed, noise-shaping SAR ADCs have unrivaled energy and area efficiencies. Recently-published noise-shaping SAR ADCs demonstrate audio-level precision. This presentation explains the basics of noise-shaping SAR and discusses techniques to extend bandwidth and resolution.

Bio: Michael P. Flynn received the Ph.D. degree from Carnegie Mellon University in 1995. From 1995 to 1997, he was a Member of Technical Staff with Texas Instruments, Dallas, TX. During the four years from 1997 to 2001, he was with Parthus Technologies, Cork, Ireland. Since 2001, Dr. Flynn has been with the University of Michigan and is currently Professor. His technical interests are in RF circuits, data conversion, serial transceivers, and biomedical systems. He is a 2008 Guggenheim Fellow. He received the 2011 Education Excellence Award, 2010 College of Engineering Ted Kennedy Family Team Excellence Award, 2016 Faculty Achievement Award, and also the 2005-2006 Outstanding Achievement Award. He received the NSF Early Career Award in 2004. Dr. Flynn was Editor-in-Chief of the IEEE Journal of Solid-State Circuits from 2013 to 2016. He is a former Distinguished Lecturer of the IEEE Solid-State Circuits Society. He served as Associate Editor of the IEEE Journal of Solid-State Circuits (JSSC) and of the IEEE Transactions on Circuits and Systems. He is chair of the ISSCC Data Conversion Committee. He formerly served on the Technical Program Committees of ESSCIRC, A-SSCC, and the Symposium on VLSI Circuits.

Abstract:  This paper presents an overview of energy-efficient techniques intended for the readout of Wheatstone bridge sensors. Apart from energy-efficiency, such bridge-to-digital converters (BDCs) must achieve low input-referred offset, drift and noise; high gain accuracy, stability and linearity; as well as high immunity to power-supply and common-mode variations. Various BDC architectures will be discussed, beginning with classical ones in which an instrumentation amplifier is followed by an analog-to-digital converter (ADC), and moving on to more recent ones, which attempt to reduce complexity by eliminating the instrumentation amplifier and connecting an ADC directly to a bridge. The performance of these topologies, and in particular their energy-efficiency, will be compared and summarized.

Bio: Kofi Makinwa is a Professor at Delft University of Technology, Delft, The Netherlands. Before that he was a research scientist at Philips Research Laboratories in Eindhoven, The Netherlands (1989 to 1999). He holds B.Sc. and M.Sc. degrees (1985, 1988) from Obafemi Awolowo University, Ife, Nigeria, an M.E.E. degree (1989) from the Philips International Institute, Eindhoven, The Netherlands and a Ph.D. degree (2004) from Delft University of Technology, Delft, The Netherlands. His main research interests are the design of precision analog circuits and sensor interfaces. This has resulted in 16 books, over 250 technical papers and over 30 patents. He is the co-recipient of 16 best paper awards, from the JSSC, ISSCC, VLSI, ESSCIRC and Transducers, among others, and is an ISSCC top-10 contributor. Prof. Makinwa has been on the program committees of several IEEE conferences, and has served the Solid-State Circuits Society as a distinguished lecturer and as a member of the Adcom. He is currently.the Analog Subcom chair of the ISSCC, a member of the editorial board of the Proceedings of the IEEE and a co-organizer of the Advances in Analog Circuit Design workshop and the Sensor Interfaces Meeting. He is an IEEE Fellow and a member of the Royal Netherlands Academy of Arts and Sciences.

Abstract:  On-chip implementation of a timing reference has been gaining more attention as it offers great opportunities for miniaturized system and lower cost. Among various candidates for extracting controllable time without bulky quartz-crystals, RC has been preferred over LC and ring-based ones in building integrated oscillators using CMOS technologies. However, challenges should still be taken in circuit design for widespread use of the RC oscillator as a wake-up timer in ultra-low-power sensor node or references for wireless and wired communications. Depending on application, power consumption, phase noise and jitter are specifically emphasized while commonly necessitating the long-term frequency stability. This talk reviews fundamentals of open-loop and closed-loop circuit implementations of the RC oscillator and performance-limiting trade-off factors. Recent trends of temperature compensation techniques will be also addressed with implementation examples.

Bio: Jae-Yoon Sim received the B.S., M.S., and Ph.D. degrees in electrical engineering from Pohang University of Science and Technology (POSTECH) in 1993, 1995, and 1999, respectively. From 1999 to 2005, he was a Senior Engineer with Samsung Electronics. In 2005, he joined POSTECH, where he is currently a Professor. From 2017 to 2019, he was the Director of the Joint Research Lab. nominated by the Korea Institute of Science and Technology. Since 2019, he has been the Director of the Scalable Quantum Computer Technology Platform Center sponsored by the Ministry of Science and ICT of Korea. His research interests include frequency generation, sensor interface circuits, serial links, data converters and quantum computing. Dr. Sim was a co-recipient of the ISSCC Takuo Sugano Award in 2001. In 2020, he received the Science of the Month Award sponsored by Ministry of Science and ICT of Korea. He was an IEEE Distinguished Lecturer from 2018 to 2019. He served on the Technical Program Committees for the ISSCC, VLSI Symposium and A-SSCC.

Abstract: This course will provide an in-depth discussion on the ultra-low power RF circuit transceiver and architecture design for Internet-of-Things (IoT) applications.  By 2025, there will be up to 100 billion wireless sensor devices connected to IoT, and the cost of replacing or recharging the batteries will become one of the bottlenecks in the massive deployment of remote sensors.  With such a strong demand on extending the battery lifetime of these IoT devices, ultra-low power RF transceivers are the key to achieving the final goal of autonomous operation for > 10 years. To address the challenges in IoT, the design requirements of one popular IoT protocol – Bluetooth Low Energy (BLE) – will be discussed. The design considerations and advancement of all-digital frequency synthesizers, one of the most critical building blocks in low-power RF transceivers, will also be addressed.

Bio: Yao-Hong Liu received his Ph.D. degree from National Taiwan University, Taiwan, in 2009. He was with Terax, Via Telecom (now Intel), and Mobile Devices, Taiwan, from 2002 to 2010, working on Bluetooth, WiFi and cellular wireless SoC products. Since 2010, he joined imec, the Netherlands. His current position is Principal Member of Technical Staff, and he is leading the development of the ultra-low power (ULP) RFIC design. His research focuses are energy-efficient wireless transceivers and radar for IoT and healthcare applications. He currently serves as a technical program committee of the IEEE ISSCC and RFIC Symposium.

Abstract: CMOS based high-speed serial electrical links continue to push the data rate forward with most recent realizations achieving over 100Gb/s at very good power efficiencies. Solutions for doubling the data rate of next generation serial links are however uncertain given the challenges of Moore’s Law and the fundamental Shannon capacity limit of the commonly used electrical channels. In this presentation, we will review the current state-of-the-art and discuss potential future options for high-density and low power wireline high-speed serial data communications, covering both electrical and optical links for server and networking applications.

Bio: Mounir Meghelli received the M.S. degree in electronics and automatics from the University of Paris Orsay in 1992 and the Engineering degree in telecommunication from the ENST-Paris, in 1994. He received his Ph.D. degree from the University of Paris VI after a 4 year research program with the CNET France Telecom Research Center, working on the design of high-speed ICs for optical communications in GaAs and InP HBT technologies. From 1998 to 2005, he joined the IBM T.J. Watson Research Center as a Research Staff Member working on the design of high frequency ICs in SiGe BiCMOS and CMOS technologies for wireline and wireless applications. From 2006 to 2011, he joined the IBM Server and Technology Group where he held a position of Senior Technical Staff Member position leading the design of advanced serial links for storage, networking and server applications. Since 2012, he has been managing the Mixed Signal Communication IC Design group at the IBM T.J. Watson Research Center.

Abstract: The last twenty years has seen an incredible explosion of adaptive circuit and system techniques, especially in the area of high-performance microprocessor design. While general purpose microprocessors continue to be essential components of any computing platform, their programmability and inherent flexibility cause them to have less performance, and less power efficiency, as compared to more structured designs such as GPUs, FPGAs, and ASICs. This deficiency has driven a significant amount of design effort to provide adaptive techniques in hardware to maximize the performance delivered, significantly improve power efficiency, and dramatically increase battery life. This talk will summarize the last twenty years of innovation, including topics such has voltage & frequency scaling, power gating, droop mitigation techniques, methods to mitigate process and environmental variation, as well as design and system-level mechanisms to enable reliability-aware performance optimizations. The talk will conclude by prognosticating what techniques we may see in future products.

Bio: Thomas Burd received the B.S, M.S, and Ph.D. degrees in electrical engineering and computer science from the University of California at Berkeley, in 1992, 1994, and 2001, respectively. He was a Consultant with multiple startups in Silicon Valley. In 2005, he joined Advanced Micro Devices, Santa Clara, CA, USA, where he has worked on multiple generations of high-performance x86 cores (including the Bulldozer and Zen families of cores) in physical design architecture, design for reliability, power delivery, and analysis methodology. He is currently a Senior Fellow Design Engineer and Physical Design Architect for the next-generation Zen core. He has authored over 25 conference and journal publications, in addition to the book Energy Efficient Microprocessor Design. He is an inventor of five U.S. patents. Dr. Burd has been serving on the ISSCC Technical Program Committee since 2017, where he is current the Digital Architectures and Systems Subcommittee Chair. He served on the Technical Program Committee for the Symposium on Very Large Scale Integration Circuits from 2012 to 2015, ICCAD from 2003 to 2005, and Hot Chips in 1996. He was a recipient of the 2001 ISSCC Lewis Winner Award for the Best Conference Paper and the 1998 Analog Devices Outstanding Student Award for recognition of excellence in IC design. He is a Senior Member of the IEEE.

Abstract: Embedded memory continues to be the key defining component for modern SoC. As applications become more data centric, the performance of SoC for future abundant data computing is increasingly constrained by the bandwidth and energy of accessing data from memory. Alternative memory technologies and computing architectures are been actively explored to address these challenges, including the emerging memory technologies and in-memory computing. In this short course, the present status and key design considerations for various emerging memory technologies will be reviewed. The latest development and challenges for in-memory computing that exploit structural alignment of 2D SRAM or emerging memory arrays for energy-efficient matrix-vector multiplication will be discussed.

Bio: Yih Wang received his Ph.D. degree in electrical and computer engineering from University of Florida, Gainesville. He joined Intel’s logic technology development group in 2001 and was a Sr. Principal Engineer, leading the development of critical technologies for a variety of embedded memories, including embedded SRAM, DRAM, STT-MRAM and ReRAM. He received three Intel Achievement Awards for his contributions on development of embedded SRAM and DRAM technologies. He is currently a director in the design and technology platform group at TSMC. He has authored and co-authored more than 40 journal and conference publications and has more than 70 issued and pending U.S. patents.