Test of Time Award

Test of Time Award Honorees

True to its name, the Test of Time Award recognizes papers that have established their significance in history by standing the test of time. It is set up to honor impactful papers and promote their recognition in the Symposia’s community.

An award will be given at each conference to one paper in each track which has had a lasting impact on the field and was published 10 or more years ago.


Since this is our inaugural year, we had many outstanding and worthy candidates. As a result, after very careful consideration and numerous discussions, we decided to make an exception this year, and selected two papers for each track to receive the Award.

D. B. Scott, W.R. Hunter, S. Shichijo, “A New Transmission Line Model For Silicided Diffusions: Impact On The Performance Of Vlsi Circuits,” Symp. VLSI Technology, paper 6-5, pp. 94 – 95 (1981).


Prior to this paper at the first VLSI Symposium in 1981, silicides were only used on the polysilicon gates in memory cells. These were typically WSi2 which had high sheet resistance, and was not considered suitable for silicon cladding. Scott’s work was important because it described the use of silicides on the drain and source contacts to reduce both sheet and contact resistance countering the increased contact resistance due to the shallow drain/source junctions required for advanced CMOS scaling. They built an ingenious model of the silicided structure, and used it to model the effects of the silicide cladding. Their simulation results showed that delays could be reduced by a factor of 10 for PMOS and 2x for NMOS. This was a key motivator for developing silicide cladded diffusions which were demonstrated at subsequent conferences by researchers from many companies. Silicides have been a huge factor in the continuation of transistor scaling over multiple decades and the results in this paper have had a significant influence on the industry over the 40 years since its publication.

R. Kirisawa, S. Aritome, R. Nakayama, T. Endoh, R. Shirota, F. Masuoka,“A NAND structured cell with a new programming technology for highly reliable 5V-only FLASH EEPROM,” Symp. VLSI Technology, paper T11-3, pp. 129 – 130 (1990).


The paper by Kirisawa, Aritome, Nakayama, Endoh, Shirota, and Masuoka is the first paper that described the write/erase programming of NAND Flash memory utilizing the Fowler-Nordheim (FN) tunneling injection of electrons between the floating gate and the substrate (known as channel FN tunneling). Prior to this paper, programming of NAND Flash memory was accomplished by carrier injection at the drain, a process that non-uniformly over-stressed the oxide near the drain. The uniform write and erase performed by properly biasing the p-well was adopted in this paper for NAND Flash memory to significantly improve the retention and endurance of NAND Flash memory. This work paved the way for broad adoption of NAND Flash memory. This write/erase method is still broadly adopted in today’s NAND Flash products. As such, this paper does stand the test of time.

T. Tanaka, Y. Tanaka, H. Nakamura, H. Oodatra, S. Aritome, R. Shirota, F. Masuoka, “A quick intelligent program architecture for 3V-only NAND-EEPROMs,” Symp. VLSI Circuits, paper 3-1, pp. 20 – 21 (1992).


The paper by T. Tanaka, Y. Tanaka, Nakamura, Oodaira, Aritome, Shirota, and Masuoka proposed an on-chip verify-programming scheme to optimize the programming pulse/voltage on a bit-by-bit basis so as to realize tight threshold voltage distribution of NAND Flash memory. Write-verify programming is accomplished by first applying short programming pulses, then states of the cells are compared with loaded program data to optimize the programming time in each cell. Prior to this work, cell data were downloaded to a circuit outside of the memory chip to make the comparison with the intended program data. However, the scheme proposed in this paper enabled verify-programming closure inside the NAND chip by adding two transistors only to the sense-amplifier circuit. Accordingly, this technology has become the de-facto standard method, and is still indispensable in today’s NAND Flash products. As such, this paper does stand the test of time.

T. Sakata, M. Horiguchi and K. Itoh, “Subthreshold-Current Reduction Circuits For Multi-Gigabit DRAM's,” Symp. VLSI Circuits, paper 5-3, pp. 45 – 46 (1993).


In the early 1990s, DRAM process technology drove the process scaling roadmap. There were many issues as 1 μm feature sizes were being approached, and one of the biggest problems was the off-current due to drain-source punch through and drain-induced-barrier-lowering (DIBL). While common to us today, these were new phenomena at that time and led many experts to predict the imminent end of scaling. This paper is the earliest description of using circuit techniques to mitigate leakage current featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder. They demonstrated a drastic reduction even for the active current of a 16 Gbit DRAM by 10x which was a huge number at that time. These techniques of using header and footer switches and multiple voltage domains formed the basis of power management schemes developed over the subsequent years to enable ultra-low power chips to be built in deep submicron CMOS technologies which generally have higher off-state leakage currents. Many challenges still remained to be solved especially for power management in complex system-on-chip ICs, but the main concept described in this paper gave circuit designers control of the leakage problem, and enabled device technology scaling to continue aggressively for three more decades.