Test of Time Award
Test of Time Award Honorees
True to its name, the Test of Time Award recognizes papers that have established their significance in history by standing the test of time. It is set up to honor impactful papers and promote their recognition in the Symposia’s community.
An award will be given at each conference to one paper in each track which has had a lasting impact on the field and was published 10 or more years ago.
- 2024
-
C. Patrick Yue and S. Simon Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's”, Sump. VLSI Circuits, Paper 12-1, pp. 85-86 (1997).
Citation:
C. Patrick Yue (eepatrick@ust.hk)This paper in 1997 introduced the first on-chip inductor with a patterned ground shield(PGS) inserted between the spiral inductor and the silicon substrate. PGS’s were realized in standard CMOS technologies using poly-silicon layer without additional processing steps – this was a key factor that drives its adoption and proliferation in low cost RFIC’s. PGS’s increase the inductor quality factor, reduce the substrate noise coupling, and improve the inductor model accuracy by decoupling the lossy silicon substrate. Over the years, PGS’s have become a de facto feature for on-chip inductors and are widely adopted.
Leland Chang, David M. Fried, Jack Hergenrother, Jeffrey W. Sleight, Robert H. Dennard, Robert K. Montoye, Lidija Sekaric, Sharee J. McNab, Anna W. Topol, Charlotte D. Adams, Kathryn W. Guarini, and Wilfried Haensch, ” Stable SRAM Cell Design for the 32 nm Node and Beyond,” Symp. VLSI Technology, paper 8A-2, pp. 128-129 (2005).
Citation:
Leland Chang (lelandc@us.ibm.com)This paper in 2005 introduced the first publication of an 8T-SRAM cell with separate read stack, enables stability for future technologies due to variability and decreasing power supply voltages. The proposed 8T-SRAM provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. This cell is widely used in high-speed applications today and is a standard offering of foundries in advanced technology nodes.
- 2023
-
D. J. Frank, Y. Taur, M. Ieong, H.-S. P. Wong, "Monte Carlo Modeling of Threshold Variation due to Dopant Fluctuations", Symp. VLSI Technology, paper J-4, 1999.
Citation:D. J. Frank, Y. Taur, M. Ieong, H.-S. P. Wong, "Monte Carlo Modeling of Threshold Variation due to Dopant Fluctuations", Symp. VLSI Technology, paper J-4, 1999.
H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and Koji Sakui, "A CMOS Band-Gap Reference Circuit with Sub 1V Operation", Symp. VLSI Circuits, paper 19.3, 1998.
Citation:This paper proposes one of the earliest implementations of a CMOS band-gap reference circuit that can successfully operate at low voltage by applying a new resistive division technique. The commonly known "Banba Bandgap" and its subsequent variations are now in the era of sub-1V technologies quite relevant. The corresponding JSSC paper is referenced by more than 600 papers and in more than 100 patents. The full text has been downloaded more then 21000 times (IEEE Xplore).
- 2022
-
Yoshinobu Nakagome, Yoshifumi Kawamoto, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, and Kiyoo Itoh, “A. 1.5V Circuit Technology for 64Mb DRAMs”, Symp. VLSI Circuits, paper 2-5, pp. 17-18 (1990).
Citation:This paper in 1990 introduced the idea of doubling the supply voltage through on-chip capacitive charge-pump circuit to boost the gate voltage of MOS switch to increase the turn-on voltage to effectively reduce its on-resistance for low voltage DRAM applications. Many variations of switch boosters followed this paper which formed an important foundation in today’s high performance switch capacitor circuits.
Jack Kavalieros, Brian Doyle, Suman Datta, Gilbert Dewey, Mark Doczy, Ben Jin, Dan Lionberger, Matthew Metz, Willy Rachmady, Marko Radosavljevic, Uday Shah, Nancy Zelick, Robert Chau, ”Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering,” Symp. VLSI Technology, paper 7-1, pp. 50-51 (2006).
Citation:Strained silicon and high-k gate dielectrics with metal gates were introduced to high volume manufacturing in 2003 and 2007 respectively, while FinFETs were still the subject of research at that time. This pioneering work in 2006 was the first demonstration of FinFETs combined with the other two boosters – uniaxial strained silicon and high-k/metal gate, a combination that would later dominate the industry.
Hiroyasu Tanaka, Masaru Kidoh, Katsunori Yahashi, Mitsuhiro Omura, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Mitsuru Sato, Yuzo Nagata, Yasuyuki Matsuoka, Yoshihisa Iwata, Hideaki Aochi, Akihiro Nitayama, “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” Symp. VLSI Technology, paper 2-2, pp. 14-15 (2007)
Citation:This paper in 2007 introduced a novel 3D NAND flash memory array architecture and method of patterning multiple layers of control gates with a single lithography step. The novel concept limited the number of lithography steps and the layout area used for driver transistors, making 3D NAND Flash commercially viable and enabled the industry to steadily increase 3D NAND storage capacity.
T. Sakata, M. Horiguchi and K. Itoh, “Subthreshold-Current Reduction Circuits For Multi-Gigabit DRAM's,” Symp. VLSI Circuits, paper 5-3, pp. 45 – 46 (1993).
Citation:In the early 1990s, DRAM process technology drove the process scaling roadmap. There were many issues as 1 μm feature sizes were being approached, and one of the biggest problems was the off-current due to drain-source punch through and drain-induced-barrier-lowering (DIBL). While common to us today, these were new phenomena at that time and led many experts to predict the imminent end of scaling. This paper is the earliest description of using circuit techniques to mitigate leakage current featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder. They demonstrated a drastic reduction even for the active current of a 16 Gbit DRAM by 10x which was a huge number at that time. These techniques of using header and footer switches and multiple voltage domains formed the basis of power management schemes developed over the subsequent years to enable ultra-low power chips to be built in deep submicron CMOS technologies which generally have higher off-state leakage currents. Many challenges still remained to be solved especially for power management in complex system-on-chip ICs, but the main concept described in this paper gave circuit designers control of the leakage problem, and enabled device technology scaling to continue aggressively for three more decades.
- 2021
-
Since this is our inaugural year, we had many outstanding and worthy candidates. As a result, after very careful consideration and numerous discussions, we decided to make an exception this year, and selected two papers for each track to receive the Award.
D. B. Scott, W.R. Hunter, S. Shichijo, “A New Transmission Line Model For Silicided Diffusions: Impact On The Performance Of Vlsi Circuits,” Symp. VLSI Technology, paper 6-5, pp. 94 – 95 (1981).
Citation:Prior to this paper at the first VLSI Symposium in 1981, silicides were only used on the polysilicon gates in memory cells. These were typically WSi2 which had high sheet resistance, and was not considered suitable for silicon cladding. Scott’s work was important because it described the use of silicides on the drain and source contacts to reduce both sheet and contact resistance countering the increased contact resistance due to the shallow drain/source junctions required for advanced CMOS scaling. They built an ingenious model of the silicided structure, and used it to model the effects of the silicide cladding. Their simulation results showed that delays could be reduced by a factor of 10 for PMOS and 2x for NMOS. This was a key motivator for developing silicide cladded diffusions which were demonstrated at subsequent conferences by researchers from many companies. Silicides have been a huge factor in the continuation of transistor scaling over multiple decades and the results in this paper have had a significant influence on the industry over the 40 years since its publication.
R. Kirisawa, S. Aritome, R. Nakayama, T. Endoh, R. Shirota, F. Masuoka,“A NAND structured cell with a new programming technology for highly reliable 5V-only FLASH EEPROM,” Symp. VLSI Technology, paper T11-3, pp. 129 – 130 (1990).
Citation:The paper by Kirisawa, Aritome, Nakayama, Endoh, Shirota, and Masuoka is the first paper that described the write/erase programming of NAND Flash memory utilizing the Fowler-Nordheim (FN) tunneling injection of electrons between the floating gate and the substrate (known as channel FN tunneling). Prior to this paper, programming of NAND Flash memory was accomplished by carrier injection at the drain, a process that non-uniformly over-stressed the oxide near the drain. The uniform write and erase performed by properly biasing the p-well was adopted in this paper for NAND Flash memory to significantly improve the retention and endurance of NAND Flash memory. This work paved the way for broad adoption of NAND Flash memory. This write/erase method is still broadly adopted in today’s NAND Flash products. As such, this paper does stand the test of time.
T. Tanaka, Y. Tanaka, H. Nakamura, H. Oodatra, S. Aritome, R. Shirota, F. Masuoka, “A quick intelligent program architecture for 3V-only NAND-EEPROMs,” Symp. VLSI Circuits, paper 3-1, pp. 20 – 21 (1992).
Citation:The paper by T. Tanaka, Y. Tanaka, Nakamura, Oodaira, Aritome, Shirota, and Masuoka proposed an on-chip verify-programming scheme to optimize the programming pulse/voltage on a bit-by-bit basis so as to realize tight threshold voltage distribution of NAND Flash memory. Write-verify programming is accomplished by first applying short programming pulses, then states of the cells are compared with loaded program data to optimize the programming time in each cell. Prior to this work, cell data were downloaded to a circuit outside of the memory chip to make the comparison with the intended program data. However, the scheme proposed in this paper enabled verify-programming closure inside the NAND chip by adding two transistors only to the sense-amplifier circuit. Accordingly, this technology has become the de-facto standard method, and is still indispensable in today’s NAND Flash products. As such, this paper does stand the test of time.
T. Sakata, M. Horiguchi and K. Itoh, “Subthreshold-Current Reduction Circuits For Multi-Gigabit DRAM's,” Symp. VLSI Circuits, paper 5-3, pp. 45 – 46 (1993).
Citation:In the early 1990s, DRAM process technology drove the process scaling roadmap. There were many issues as 1 μm feature sizes were being approached, and one of the biggest problems was the off-current due to drain-source punch through and drain-induced-barrier-lowering (DIBL). While common to us today, these were new phenomena at that time and led many experts to predict the imminent end of scaling. This paper is the earliest description of using circuit techniques to mitigate leakage current featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder. They demonstrated a drastic reduction even for the active current of a 16 Gbit DRAM by 10x which was a huge number at that time. These techniques of using header and footer switches and multiple voltage domains formed the basis of power management schemes developed over the subsequent years to enable ultra-low power chips to be built in deep submicron CMOS technologies which generally have higher off-state leakage currents. Many challenges still remained to be solved especially for power management in complex system-on-chip ICs, but the main concept described in this paper gave circuit designers control of the leakage problem, and enabled device technology scaling to continue aggressively for three more decades.