PROGRAM

Attendee Access to Sessions:

• If you register by 8am EDT, you will get access by 9am EDT.
• If you register from 8am to 4pm EDT, you will get access by 5pm.
• If you register after 4pm EDT, you will get access by 9am EDT the next day.

The VLSI Symposia on Technology and Circuits will feature an exciting program of live events, as summarized below. This includes 2 plenary sessions, 4 panel discussions, 3 workshops, and 25 Executive Sessions. The goal of Executive Sessions in the VLSI Symposia is to foster a discussion about the current state and future of the field. All conference participants are welcome to join these meetings and contribute with insight and questions.

You can download the .ics calendar invite for all the events here, or for individual events by pressing the 🗓️ icon below.

• SC1 (Technology) – Future of Scaling for Logic and Memory
• SC2 (Joint) – Heterogeneous Integration – To Boldly Go Where No Moore Has Gone Before
• SC3 (Circuits) – Trends and Advancements in Circuit Design

• FF – Technologies and Circuits for Edge Intelligence

• LT – Do You Really Know What Is In Your Computer? Perspectives on Verifiable Supply Chains

• P2 – Joint Panel – 40 Years of VLSI to Enable the Future of Computing

• JFS1 – Silicon Photonics
• JFS2 – 5G/mm-Wave
• JFS3 – STCO/DTCO
• JFS4 – Devices and Circuits for AI/ML
• JFS5 – Heterogeneous Integration

• Demo Session

• THL – Highlight Session
• TC1 – Advanced Si CMOS Devices
• TC2 – Ge and SiGe Devices
• TC3 – Advanced Processing
• TF1 – FeFETs
• TF2 – Ferroelectric Memory and Capacitors
• TH1 – 3D Packaging
• TH2 – Semiconducting Oxides for 3D Integration
• TH3 – Si Technologies for 3D Integration
• TM1 – Memory – NAND/NOR/PCM
• TM2 – RRAM
• TM3 – STT MRAM
• TMFS – MRAM Future – Opportunities Beyond STT
• TN1 – New Devices and Applications
• TN2 – Quantum Computing

• CA1 – Machine Learning
• CA2 – Visual Processing & AI
• CA3 – Digital Systems
• CB1 – Biomedical Sensors
• CB2 – Image Sensor & Imaging Techniques
• CB3 – Physical Sensors
• CB4 – Front-Ends for Sensor Interfaces
• CC1 – Circuits for Security and Safety
• CC2 – Adaptive Clocking and Power Delivery
• CD1 – High-Speed Data Converters
• CD2 – Data Converter Techniques
• CF1 – Advanced PLLs
• CF2 – RF & mm-Wave Circuits
• CF3 – IoT and Wireless Receivers
• CF4 – Low Power Oscillators
• CM1 – Advanced SRAM Design
• CM2 – Emerging Memory Design
• CM3 – Energy Efficient Memory Design
• CP1 – Amplifiers
• CP2 – Voltages References and Wireless Power
• CP3 – Power Converters
• CW1 – Ultra-High-Speed Wireline
• CW2 – Wireline Techniques

• WS1 – Analog Computing Technologies and Circuits for Efficient Machine Learning Hardware
• WS2 – Know Where You Are Going; Metrology In the New Age of Semiconductor Manufacturing
• WS3 – Quantum Computers for Electrical Engineers

Panels

• P2 – Joint Panel – 40 Years of VLSI to Enable the Future of Computing
• SSCS/EDS Sponsored Diversity Panel: Cultivating Engineering Confidence
• Workshop Panel and Q&A – Analog Computing Technologies and Circuits for Efficient Machine Learning Hardware

Mentoring Event

• EDS/SSCS YP Event

Workshops

• WS1 – Analog Computing Technologies and Circuits for Efficient Machine Learning Hardware
• WS2 – Know Where You Are Going; Metrology In the New Age of Semiconductor Manufacturing
• WS3 – Quantum Computers for Electrical Engineers
• Workshop Panel and Q&A – Analog Computing Technologies and Circuits for Efficient Machine Learning Hardware
• Workshop Panel and Q&A – Know Where You Are Going; Metrology In the New Age of Semiconductor Manufacturing
• Workshop Panel and Q&A – Quantum Computers for Electrical Engineers