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The following press materials are available for pre-conference publicity for the 2020 Symposia on VLSI Technology & Circuits

Press Releases


VLSI 2020 Symposia Program Release

The 2020 Symposia on VLSI Technology & Circuits Goes Virtual

VLSI Symposia 2020 Call for Papers (English)

2020 Lead Release (English)

2020 Technical Tip Sheet (English)

2020 Tipsheet images (w/captions & hi-res)(English)

2020 Tipsheet without images (Word Doc) (English)

2020 Symposia Lead Release (Japanese)

2020 Symposia Tip Sheet Technical Terms (Japanese)

2020 Symposia Tipsheet (Japanese)

2020 Symposia Lead Release (Simplified Chinese)

2020 Symposia Tip Sheet Technical Terms (Simplified Chinese)

2020 Symposia Tipsheet (Simplified Chinese)

2020 Symposia Lead Release (Korean)

2020 Symposia Tip Sheet Technical Terms (Korean)

2020 Symposia Tipsheet (Korean)

2020 Symposia Lead Release (Traditional Chinese)

2020 Symposia Tip Sheet Technical Terms (Traditional Chinese)

2020 Symposia Tipsheet (Traditional Chinese)

Images


Hilton Hawaiian Village Rainbow Tower

2020 VLSI Symposium Technology logo

2020 VLSI Symposium Circuits logo

Paper Highlights VLSI 2020


Paper T-N3-1
“Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperaturesdown to 100mK for Quantum Computing” B. Cardoso Paz et al., CEA-Leti/STMicroelectronics/Institut Néel

Paper T-M3-1
“Scalability of Quad Interface p-MTJ for 1Xnm STT-MRAM with 10ns Low Power Write Operation, 10-years Retention and Endurance >1011” S. Miura et al., Tohoku University

Paper T-M1-1
“An Extremely Scaled Hemi-Cylindrical (HC) 3D NAND Device with Large Vt Memory Window (>10V) and Excellent 100K Endurance” P-Y. Du et al., Macronix International

Paper T-HL-6
“Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5nm Node” A. Gupta et al., imec

Paper T-M1-1
“An Extremely Scaled Hemi-Cylindrical (HC) 3D NAND Device with Large Vt Memory Window (>10V) and Excellent 100K Endurance” P-Y. Du et al., Macronix International

Paper T-HL-5
“Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact Over Active Gate (COAG) for Highly Scaled CMOS Technology” K. Cheng et al., IBM Research

Paper T-HL-4
“A Monolithic 3D Integration of RRAM Array with Oxide Semiconductor FET for In-memory Computing in Quantized Neural Network AI Applications” J. Wu et al., The University of Tokyo

Paper T-HL-3
“An Optically Sampled ADC in 3D Integrated Silicon-Photonics/65nm CMOS”, N. Mehta et al., UC Berkeley/MIT/LBNL/CNSE

Paper T-HL-2
“GaN and Si Transistors on 300mm Si(111) enabled by 3D Monolithic Heterogeneous Integration” H.W. Then et al, Intel Corp

Paper T-HL-1
“5G and AI Integrated High Performance Mobile SoC Process-Design Co-Development and Production with 7nm EUV FinFET Technology” J. Deng et al., Qualcomm Technologies/ Samsung Electronics

Paper T-H2-2
“Surrounding Gate Vertical-Channel FET with Gate Length of 40nm Using BEOL Compatible High-Thermal-Tolerance In-Al-Zn Oxide Channel”, H. Fujiwara et al., Kioxia Corp

Paper T-H1-1
“Low Temperature SoICTM Bonding and Stacking Technology for 12/16-Hi High Bandwidth Memory (HBM)” C.H. Tsai, et al., Taiwan Semiconductor Manufacturing Company

Paper T-F2-5
“Fast Thermal Quenching on the Ferroelectric Al:HfO2 Thin Film with Record Polarization Density and Flash Memory Application” B. Ku et al., Hanyang University

Paper T-C1-2
“7-Level-Stacked Nanosheet GAA Transistors for High Performance Computing” S. Barraud et al., CEA-LETI-MINATEC

Paper JFS5-3
“A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-chip Package with F-Chip of Toggle 4.0 Specification for High performance and High capacity Storage Systems” Jang-woo Lee, et al., Samsung Electronic

Paper JFS2-6
“An RF Transceiver with Full Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS” Sangwook Han, et al., Samsung Electronics

Paper JFS1-3
“A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS” Jonathan E. Proesel, et al., IBM

Paper C-F2-2
“A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation” Jian Pang, et al., Tokyo Institute of Technology & NEC Corporation

Paper C-B3-2
“A Pressure Sensing System with ±0.75mmHg (3σ) Inaccuracy for Battery-Powered Low Power IoT applications” Seokhyeon Jeong, et al., University of Michigan & CubeWorks

Paper C-B2-2
“A 36-channel SPAD-integrated Scanning LiDAR Sensor with Multi-event Histogramming TDC and Embedded Interference Filter” Hyeongseok Seo, et al., Sungkyunkwan University

Paper C-B1-2
“An Artificial Iris ASIC with High Voltage Liquid Crystal Driver, 10nA Light Range Detector and 40nA Blink Detector for LCD Flicker Removal” Bogdan C. Raducanu, et al., imec

Paper C-A3-5
“32 GHz 6.5 mW Gate-Level-Pipelined 4-bit Processor using Superconductor Single-Flux-Quantum Logic” Koki Ishida, et al., Kyushu University & Nagoya University

Paper C-A1-1
“A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference” Jinwook Oh, et al., IBM

Paper C-2-1
“A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor” Vijay Kiran Kalyanam, et al., Qualcomm Technologies, Inc. & University of Texas

Editor Contact


Chris Burke
Media Relations Director
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chris.burke@btbmarketing.com

Deidre Artis
Conference Manager
vlsisymposium@ieee.org