2025 Symposium on
VLSI Technology and Circuits

Plenary Session 1

Date & Time: 8:00A.M.-10:00A.M. on June 10 (Tue)

PL1-1

Driving Innovation in DRAM Technology: Towards a Sustainable Future

Dr. Seon-Yong Cha

CTO, Head of R&D, SK hynix

Dr. Seon-yong Cha is the Chief Technology Officer (CTO) and Head of R&D at SK hynix, responsible for driving the company’s technological competitiveness. Since joining Hyundai Electronics (now SK hynix) in 1995, he has played a key role in advancing memory technologies, starting with improvements to DRAM transistors that enhanced overall device performance. In 2015, Dr. Cha spearheaded the development of 1xnm DRAM and introduced the concept of platform-based Tech. development, laying the foundation for SK hynix’s leadership in memory technology. Building on this success, he oversaw DRAM product development starting in 2019, during which he successfully led the mass production of industry-leading HBM2E and the launch of the world’s first DDR5 DRAM, elevating the company’s product competitiveness to a new level. Since 2021, Dr. Cha has led the R&D Center, where he has refined SK hynix’s technology roadmap (HTRS) to enhance its completeness. By proactively preparing key technologies, he has addressed significant technical challenges and reinforced SK hynix’s leadership in the memory industry. Currently, as CTO, Dr. Cha is dedicated to strengthening SK hynix’s technological leadership across all areas of development, including DRAM, NAND, emerging memory, and CIS. Dr. Seon-yong Cha holds bachelor’s, master’s, and doctoral degrees in Electrical and Electronic Engineering from the Korea Advanced Institute of Science and Technology (KAIST).

Abstract:
Since the introduction of the 6F2 Buried Gate Scheme in the early 2010s, DRAM technology has evolved based on platforms that can be continuously scaled down to 10nm technology. Beyond 10nm, however, the evolution of DRAM technology has reached an inflection point where it is difficult to build scalable platforms using existing cell schemes and meet the high performance demands of the AI era. In response to the inflection point, this presentation will review how cell schemes will change to ensure a scalable platform and describe how DRAM technology can innovate in a way that delivers new values in the era of AI.

PL1-2

Innovate VLSI for AI Growth

Dr. John Chen

Corporate Vice President of Technology and Foundry Management, NVIDIA

John Y. Chen has been the Corporate Vice President of Technology and Foundry Management at NVIDIA Corporation since 2004.  Prior to that, Dr. Chen spent 10 years at TSMC.  He created and ran the R&D at TSMC, Taiwan. Subsequently, he built and ran fab operations of WaferTech in Camas, WA, then served as the Vice President of Business Development in the last year at WaferTech.
Earlier in his career at Hughes Research Lab and Xerox Palo Alto Research Center, he has contributed more than 100 refereed journal articles, most published by IEEE including the papers presented at the VLSI Symposium in 1982 Oiso Japen and other years. He has been invited to give numerous speeches including the plenary speeches in 1996 IEDM and 2009 IEDM, and luncheon speech in 2018 IEDM. He wrote a textbook on “CMOS Devices and Technology for VLSI,” published by Prentice Hall, a part of Simon & Schuster today. He was elected to the IEEE Fellow in 1992 for “leadership in and contributions to CMOS device and process technology”.
In the 80’s, he has served on the Technical Advisory Board of ITRI/ERSO, the incubator of Taiwan semiconductor industry including TSMC. In 2001, he became the board director of Cascade Inc. (Nasdaq:CSCD) for six years until the company was acquired by FormFactor (Nasdaq:FORM). His recent book on “Leadership in Management” was published by Nova Science Publishers, N.Y. in 2022.
Dr. Chen holds a B.S. in E.E. from National Taiwan University, an M.S. in E.E. from University of Maine, a Ph.D. in E.E. from UCLA, and a master’s degree from UCLA Anderson School on Executive Management.

Abstract:
AI is built on VLSI by the amazing Moore’s law which is ended, but we need VLSI more than ever in AI era.  So, what’s next?  It’s innovation, innovate from materials, devices, modules to systems. This speech presents the progress of VLSI from the past decade and highlights the most complicated VLSI chip today. Innovation is easier said than done. What are the criteria and barriers for success and the leadership needed to cultivate innovation?  The speaker’s career has lived through the relationship between VLSI and AI, their similarity, synergism and reinforcement that accelerates their thriving growth.  With AI taking away routine and complicated tasks, he answers the question of what should young people be doing? While AI is becoming such a powerful tool, the leaders and engineers must help to grow ethics and morality for the mankind.

Plenary Session 2

Date & Time: 8:00A.M.-10:00A.M. on June 11 (Wed)

PL2-1

Enabling Generative AI: Innovations and Challenges in Semiconductor Design Technologies

Dr. K. Lawrence Loh

Corporate Senior Vice President, MediaTek Inc.
President, MediaTek USA Inc.

Dr. Kou-Hung Lawrence Loh is a Corporate Senior Vice President at MediaTek Inc. He also serves as President of MediaTek USA, overseeing corporate strategy and advanced technologies development for the company.
In the past 30+ years Dr. Loh has dedicated to semiconductor IC design industry in Silicon Valley and Taiwan. For over 20 years he has led MediaTek's global IC design teams, contributing to development of the company’s SOCs, chipsets and key technologies. Dr. Loh has authored/coauthored dozens of technical papers and patents, and he also contributed panel talks, forums and invited keynotes at numerous globally renowned conferences and professional communities, including notably a plenary speech delivered at ISSCC 2020. He served on ISSCC ITPC and was on Steering Committee of SRC Decadal Plan for many years. Dr. Loh is currently on Steering Committee of A-SSCC, and he also serves on Board of Directors for Global Semiconductor Alliance (GSA).

Abstract:
In recent years, Generative AI has profoundly transformed a wave of revolution across all fields from our daily life to advanced science exploration. This transformation has triggered an unparalleled increase in the demand for computing, connectivity/communication, and memory/data storage across data centers, infrastructures, and edge devices. The uptick has catalyzed booming industrial investments spanning a spectrum of “hard tech” based on advanced materials, packaging and semiconductor process technologies, such as hardware accelerators, wired and wireless connectivity/communication, and heterogeneous integrations from chip to discrete levels, all supported by substantial research and development investments to embrace the AI era.
In this presentation, we will explore the frontier of cutting-edge technologies and tackle the challenges associated with the development of high-performance computing and highspeed connectivity solutions under considerations to accomplish demanding energy efficiencies. Additionally, we will address the mounting demands posed by power distribution and other engineering complexities. Our focus will highlight the pivotal role of innovation and investments to ensure the long-term sustainability in the forthcoming decades.

PL2-2

The evolution of edge AI: contextual awareness and generative Intelligence

Mr. Alessandro Cremonesi

Executive Vice President, Chief Innovation Officer, General Manager of System Research and Applications

Alessandro Cremonesi is STMicroelectronics’ Executive Vice President, Chief Innovation Officer and General Manager of STMicroelectronics’ System Research and Applications (SRA) Group. Cremonesi’s responsibilities span from global innovation coordination to corporate advanced R&D to system-solutions support for ST customers. He has been a key contributor to ST’s extensive efforts and strategy in IoT and Artificial Intelligence and, more recently, has led the creation of strategic initiatives to increase ST’s innovation capability. He has authored several technical papers and patents and is a member of the Scientific Advisory Board at IMEC.

Abstract:
We are witnessing a rapid transition from traditional AI to generative AI in the cloud. This is driving increased demands in the high-performance computing domain. However, to support this shift sustainably, edge AI technologies are advancing, including hardware accelerators (NPU) in microcontrollers and disruptive technologies like in-memory and neuromorphic computing. These developments, along with optimized large language models, enable more efficient AI and generative AI solutions for edge products. This keynote will explore the transformative potential of contextual awareness in AI for edge devices. Advanced sensing technologies and generative AI will revolutionize interactions with the world, allowing AI to adapt based on localized experiences and migrate seamlessly across devices. These innovations will drive the future of technology, making it more cognitive, generative, and interactive, ultimately leading to smarter, more connected and more sustainable solutions.