Memory Technology and Logic Technology have evolved along different paths. The emergence of new system architectures for heterogeneous compute has given new usage models for memory and potentially the need for new optimizations. Current AI/ML architectures are not well balanced with respect to memory performance and/or capacity, for instance. How will technology respond to this challenge? New memories? New architectures? Alternate technology optimization? Packaging solutions? This panel will bring together these different viewpoints to debate these questions.
Moderator: Gary Bronner, Rambus
Suburamanian Iyer (UC Los Angeles)
Vivienne Sze (Massachusetts Institute of Technology)
KC Wang (Macronix International)
Zhao Wang (Facebook)
From the second design of an op-amp or nand gate on to today designers have been trying to “automate circuit design”. Has this progressed from the Quixote quest of the past to a practical effort? Will and how well will it work? Will it replace circuit designers or assist them? We have assembled a mix of panelists with high level views and those in the trenches to assess the progress toward this goal and the effects of reaching it.
Moderator: Chris Menglesdorf, Analog Devices
Elad Alon, UC Berkeley
Linton Salmon, DARPA
Nan Sun, University of Texas at Austin
David Wentzloff, University of Michigan
Kazuo Yano, Hitachi