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Monday, June 10, 2019 (Suzaku I)

Advanced 5G Circuits, Systems and Applications

Ho-Jin. Song, POSTECH
Alvin Loke, TSMC

The course demystifies recent advances in 5G wireless circuit technologies covering transceivers, PLL, Filter, MIMO beam forming, as well as system architectures and applications.

Many mobile communication operators including NTT DOCOMO plan to launch 5G commercial services in 2019 or 2020, and it is important to identify reality of 5G in industries. In this presentation, DOCOMO’s views on reality of 5G in terms of time plan, NW migration scenarios, spectrum deployment scenarios, performance, etc. And, updates on DOCOMO’s 5G trial activities with variety of vertical industry players to create 5G applications will be presented, also. Finally, our views on further evolution of 5G will be presented.

About Takehiro Nakamura

Mr. Takehiro Nakamura joined NTT Laboratories in 1990. He is now SVP and General Manager of the 5G Laboratories in NTT DOCOMO, Inc.
Mr. Nakamura has been engaged in the standardization activities for the W-CDMA, HSPA, LTE/LTE-Advanced and 5G at ARIB in Japan since 1997. He has been the Acting Chairman of Strategy & Planning Committee of 5G Mobile Communications Promotion Forum(5GMF) in Japan since October 2014.
Mr. Nakamura has also been contributing to standardization activities in 3GPP since1999, including as a contributor to 3GPP TSG-RAN as chairman from April 2009 to March 2013.
He is also very active in standardization of C-V2X/Connected Car in ARIB and ITS Info-communications Forum in Japan. He is now a leader of Cellular System Application Task Group of ITS Info-communications Forum.

5G systems are now being launched by the leading telecommunication companies from last year for both below-6GHz and above-6GHz bands and this gives a big opportunity to the mmWave RFIC technology for mobile devices and infrastructure systems. In this presentation, we will give an overview of the mmWave RFIC technologies mainly focused on the 5G infrastructure applications. First, the RF system requirements for the 5G NR standards will be reviewed briefly. Then, we will introduce several considerations in the selection of IC process, RF architecture, chipset partition and interface, packaging and antenna connection, IC block designs, and so on, in order to achieve the best system solutions in the aspect of RF performances, power consumption, size, and cost. At the end, we will review a few IC implementation examples currently published up to date, including Samsung Network’s solutions that have been applied for the pre-5G and 5G NR basestation and CPE systems already installed in the fields.

About Sung-Gi Yang

Sung-Gi Yang received the B.S., M.S., and Ph.D. degrees in EE from Seoul National Univ. in 1992, 1994, and 1999, respectively. His doctoral research spanned from the design and fabrication of GaAs-based field-effect transistors (FETs) to the development of the high-speed and ultra-broadband circuits for the optical communication systems. In 1999, he joined Samsung System-LSI business unit, where he led a variety of BiCMOS/CMOS-based RFIC product developments in cellular and wireless connectivity applications. During 2014~2015, he was in charge of the whole wireless connectivity (WiFi/Bluetooth/GNSS) development team including the modem and software technology. From 2017, he is leading the RF Lab. in Samsung Network business unit, working on the development of mmWave RFIC solutions aiming at the 5G infrastructure applications. He was a visiting scholar in EE of Stanford Univ. during 2008~2009, pursuing the ADC technologies in wireless communications and was also involved in the development of the advanced PMIC technologies in 2016.

For more than 50 years, Moore’s law has been driving the landscape of the semiconductor industry including the mobile market mainly motivated by an economic reason, such as the increasing number of transistors per cost. The same quest remains uncompromised for the 5G era despite the proliferation of frequency bands, Carrier-Aggregation and MIMO. The 5G market is very lucrative and strategically important for many companies, but design challenges are expected to continue intensifying as more bands and CA combination keep getting added. Nevertheless, the cost efficiency formulated by Moore’s law would still be one of the most competitive advantages for any market leaders. This presentation describes 5G link requirements and beamforming system architecture. We then cover the recent silicon technology improvement to match the 5G mmWave performance requirement with advanced silicon scaling along with CMOS circuit design techniques for power-efficient implementation of mmWave applications. Finally, we review the state-of-the-art assembly technology to extend the life of Moore’s law for the mobile industry, the most stubborn industry against silicon scaling due to higher performance expectations and sizable passive components.

About Hyung-Jin Lee

Hyung-Jin Lee is a principal engineer and a group lead of Wireless Circuit Technology (WiCT) group at Intel, and he is currently directing Intel-University Research shuttle program to support advanced academic research activities worldwide. Hyung-Jin Lee received the B.S. degree in Electrical Engineering from Hanyang University in Seoul, Korea in 2000, and the M.S. and Ph.D. degrees in Electrical Engineering from Virginia Tech in Blacksburg Virginia, the United States in 2003 and 2006 respectively. He joined Intel in 2006, where he worked on PLL design for wireless and wireline communication systems and eventually expanded his expertise on RF process development and RFIC topology development optimized for Intel process technology. He is currently focusing on process solutions for next-generation high-frequency devices and RF/Analog-Mixed-Signal circuit design with advanced CMOS process technology.

In recent years, high-quality contents for VR/AR and 3D video and high data-traffic services of massive IoTs are stimulating people’s appetite and demanding 5G mobile that can provide an ultra-wide data bandwidth. In practical models of 5G network, where the interoperability between mmW-band and sub-6GHz network is the key, how efficiently cover a wide range of spectrum from hundreds MHz to mmW-band is important. Along with this, to comply with the stringent EVM requirements of high-order modulations over a wide channel bandwidth, the generation of local-oscillating (LO) signals becomes a challenging task. In this presentation, design challenges of LO-generating circuits are looked over. Then, we introduce several solutions to address these challenges. An efficient architecture that can concurrently generate ultra-low IPN mmW-band and sub-6-GHz signals is proposed. In addition, new design techniques of key building blocks, such as a reference-frequency doubler, an injection-locking frequency multiplier, a charge-pump PLL, and a digital sub-sampling PLL, are presented.

About Jaehyouk Choi

Jaehyouk Choi received the B.S. degree (summa cum laude) in electrical engineering from Seoul National University, Seoul, South Korea, in 2003, and the M.S. and Ph.D. degrees in electrical and computer engineering from Georgia Institute of Technology, Atlanta, GA, USA, in 2008 and 2010, respectively. From 2010 to 2011, he was with Qualcomm, Inc., San Diego, CA, USA, where he was involved in designing multi-standard cellular transceivers. In 2012, he joined Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, where he is currently an Associate Professor of Electrical and Computer Engineering. His research has focused on designs of low-power and high-performance RF/analog integrated circuits for emerging wireless/wired standards. He has authored or co-authored more than 50 IEEE journal and conference papers. He has served as a TPC member of IEEE ISSCC since 2017 and as a TPC member of IEEE ESSCIRC since 2016. He also has served as the country representative of Korea for the ISSCC Far-East region since 2018.

In recent years, due to high performance and multiband applications of mobile communication devices, there is an increasing need for improvement in characteristics and miniaturization of filters that are used. Acoustic filters using surface acoustic wave (SAW) and bulk acoustic wave (BAW) are widely used for smartphones. In this presentation, we will give an overview of the design and characteristics of acoustic filters provide insight into future development for 5G. First, we will review the fundamental principle of the resonator in the SAW filter and the BAW filter and its filter design, and Q value and coupling coefficient, which are key parameters required for determining the characteristics. Next, we will explain the temperature compensation technology necessary to improve the characteristics. As the number of frequency bands increases, there is interest in learning how to suppress the temperature drift of the filter, which is needed for the current filter design. We will focus on the spurious as a problem in the temperature compensating filter and its suppression method in detail. We will conclude with a discussion of examples of characteristics of acoustic filters, mainly SAW filters, incorporating these methods.

About Hiroyuki Nakamura

Hiroyuki Nakamura received B.S. and M.S. degrees in electrical engineering from Tohoku University, Japan, in 1993 and 1995, respectively, and his doctorate of engineering degrees from Chiba University in 2009. In 1995, he joined Matsushita Electric Industrial Co., Ltd., Osaka, Japan. From 2014, he transferred to Skyworks Panasonic Filter Solutions Japan Co., Ltd., a joint venture which was fully acquired by Skyworks Solutions, Inc. in 2016. He has been involved in research and development on microwave circuitry and components, especially on SAW filters for mobile communication applications. He has published over 50 papers on SAW filter and filter design and circuit. He is a member of the Technical Program Committee for The IEEE International Ultrasonics Symposium and is an IEEE Senior member

To correspond a rapid growing traffic, the specifications of 5th generation mobile network (5G) have been discussed in 3GPP. 5G NR is including mm Wave technology. The transmission loss of the traces and antennas will be drastically large in mm Wave. In this presentation, we will give two technologies for the development of mm Wave RF devices. One is low loss substrate technology and the other is packaging technology with RF-IC and antennas. In the substrate technology, not only the dielectric loss but also the metal treatment (e.g. surface roughness) will be discussed. Regarding packaging technology, the packaging structure with short trace between antennas and RF-IC will be introduced. The cost target of the devices and productivity in the factory are important for the development of the productions for commercial market (e.g. smart phone). We will conclude with a discussion of examples from industry that have include these technologies.

About Kaoru Sudo

Kaoru Sudo received his B.S., M.S. and D.E degrees in electrical and electronic engineering from Tokyo Institute of Technology, Tokyo, Japan in 2000, 2002 and 2005, respectively. From 2004 to 2006, he was a Research Fellow with Japan Society for the Promotion of Science (JSPS). After his studies, he worked for Murata Manufacturing Co., Ltd., Japan, where he is the manager of the millimeter wave antenna design group. His work has focused on the development for millimeter wave communication module design. He received the Young Engineer Award from IEICE Japan in 2005.

Beamforming is one of the central concepts in the 5th Generation wireless MIMO systems. It utilizes antenna arrays to simultaneously achieve spatial filtering of unwanted interferences and highly directional communication of desired signals. In this presentation, we will give an overview of advances in beamforming circuits, systems, and operations, by covering different architectures of analog beamforming, digital beamforming, and hybrid beamforming as well as their pros and cons in various application scenarios. Moreover, 5G mm-Wave MIMOs often rely on pencil-sharp beams to compensate high path loss, posing major challenges in transmitter/receiver alignments in reality. Further, many mobile 5G applications, such as vehicle-based sensing/communication and AR/VR, require dynamic beamforming and tracking of multiple desired signals and interferences with unknown or fast-changing AoAs in congested and complex electromagnetic (EM) environments. Therefore, we will introduce recent work on autonomous MIMO beamforming that addresses these challenges in mobile 5G systems. In addition, inevitable element coupling in an antenna array leads to beam-dependent antenna impedance variations that have profound and adverse effects on the frontend electronics. We will present some studies of such antenna variations on power amplifiers and low noise amplifiers. We will conclude with several design examples to demonstrate these beamforming architectures.

About Hua Wang

Hua Wang is an associate professor at the School of Electrical and Computer Engineering (ECE) at Georgia Institute of Technology and the director of Georgia Tech Electronics and Micro-System (GEMS) lab. Prior to that, he worked at Intel Corporation and Skyworks Solutions on mm-Wave integrated circuits and RF front-end modules. He received his M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, in 2007 and 2009, respectively. Dr. Wang is interested in innovating mixed-signal, RF, and mm-Wave integrated circuits and hybrid systems for wireless communication, radar, imaging, and bioelectronics applications. He received the DARPA Young Faculty Award in 2018, the National Science Foundation CAREER Award in 2015, and the IEEE MTT-S Outstanding Young Engineer Award in 2017, as well as many best paper awards at IEEE conferences. He held the Demetrius T. Paris Professorship from 2014 to 2018. He is a Technical Program Committee (TPC) Member for IEEE ISSCC, RFIC, CICC, and BCICTS conferences. He was the TPC Chair for IEEE CICC in 2018 and the Conference Chair in 2019. He is a Steering Committee Member for RFIC and CICC. He is a Distinguished Lecturer (DL) for the IEEE Solid-State Circuits Society (SSCS) for the term of 2018-2019. He serves as the Chair of the Atlanta’s IEEE CAS/SSCS joint chapter that won the IEEE SSCS Outstanding Chapter Award in 2014.

RF and millimeter-wave phased arrays employ multiple antennas and phase-shifting circuit elements to provide beamsteering capabilities and increased antenna gain. Test and calibration of these array is challenging, due to the large number of high-frequency inputs/outputs, the large number of phase and amplitude states, and the need for chip-level, package-level, and antenna-level characterization. Built-in self-test (BIST) can be used to address these challenges; however, solutions should ideally enable in-situ testing of the array with small test circuit overhead. In this talk, state-of-the-art approaches to phased-array BIST will first be reviewed, including on-chip versus free-space measurement, sequential versus parallel testing, scalar versus vector detection, and direct versus coded measurement. Two BIST approaches will then be presented in depth along with representative hardware results. The first approach employs an on-chip test channel to inject or extract signals from the full array to enable sequential measurement of each element’s vector response using an on-chip receiver with coherent in-phase/quadrature-phase mixers. Representative measurements indicate excellent accuracy when compared to network analyzer measurements. The second approach, called code-modulation embedded test (CoMET), uses a similar on-chip test channel, but applies code modulation using the phase-shifters to enable parallel measurement of each element’s vector response using simple power detectors. Measurements indicate that CoMET provides up to 0.3 dB gain accuracy and 1 degree phase accuracy. Further, a calibration loop employing CoMET enables a 10-GHz eight-element array which is packaged and connected to a linear antenna array to achieve seven-bit phase resolution with a near-ideal measured antenna pattern.

About Brian Floyd

Brian Floyd received the B.S., M.Eng., and Ph.D. degrees in ECE from the University of Florida in 1996, 1998, and 2001, respectively. From 2001 to 2007, he was a research staff member at IBM Research in Yorktown Heights, New York. His work at IBM included the investigation and demonstration of some of the first silicon-based 60-GHz radios. From 2007-2009, he was the manager of the wireless circuits and systems group at IBM Research, co-leading the development of 60-GHz phased-arrays. Since 2010, he has been with the ECE Department at North Carolina State University, where he is now a Professor. His research interests include phased-array transceivers, code-modulated interferometry for BIST and low-cost imaging, N-path techniques for filters and receivers, and scalable approaches to millimeter-wave packaging. He currently serves on the steering committee of the IEEE RFIC Symposium, and has served on the technical program committees for ISSCC, RFIC Symposium, and BCTM. Dr. Floyd has received a DARPA young faculty award, two best paper awards from ISSCC, two best paper awards from IBM, and is a member of the NC State Academy of Outstanding Teachers.