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Monday, June 10
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Monday, June 10
JFE Organizer: Munehiro Tada, NEC
NAE Co-organizer: Nirmal Ramaswamy, Micron
This short course highlights the key technologies that will push semiconductor performance forward through materials, advanced devices, design, materials and packaging.
This short course will give an overview of key limitations of FinFET scaling and process options to break these limitations and their challenges. We will first review the fundamental benefit of FinFET and the optimal fin geometry to maximize the benefit, including the pros and cons of fin aspect ratio and fin pitch. We will then evaluate the interaction of the gate pitch scaling and related downstream process flow, and how to optimize source/drain, contact and metal gate. To continue the scaling trend, we will list the potential enabling new materials and process capabilities and discuss their readiness for insertion into the mainstream technology nodes. Lastly, we will discuss some potential FinFET replacement options, such as gate-all-around transistors.
Mark Y. Liu joined Portland Technology Development of Intel Corporation in 1995. He held various positions including process engineer and engineering group leader in ion implantation and advanced thermal processing groups, where his work primarily focused on shallow junction technology. He later joined Portland Technology Development’s process integration group with responsibility of developing Intel’s 32nm and 14nm technology nodes. He is currently a front-end process integration manager working on 7nm technology development. Dr. Liu received his B.S. in Physics from Peking University in 1986 and his Ph.D. in Electrical Engineering from the University in Minnesota in 1995.
While dimension scaling, introduction of new materials and novel device structures has enhanced the transistor performance, the opposite is true for the copper interconnects that link these transistors. Looking into the future the relentless scaling paradigm is threatened by the limits of copper/low-k interconnects, including excessive power dissipation, insufficient communication bandwidth, and signal latency. Many of these obstacles stem from the physical limitations of copper/low-k electrical wires, namely the increase in copper resistivity, as wire dimensions and grain size become comparable to the bulk mean free path of electrons in copper and the dielectric capacitance. Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates. This talk will address effects of scaling on the performance of Cu/low-k interconnects, alternate interconnect schemes: carbon nanotubes (CNT), graphene, optical interconnect, three-dimensional (3-D) integration and heterogeneous integration of these technologies on the silicon platform. Performance comparison of these technologies with Cu/low-k interconnects will be discussed.
Krishna Saraswat is Rickey/Nielsen Chair Professor of Electrical Engineering at Stanford University. He also has an honorary appointment of an Adjunct Professor at the BITS, Pilani, India since January 2004. He received Ph.D. from Stanford University, USA in 1974 and B.E. from BITS, Pilani, India in 1968. His research interests are in new and innovative materials, structures, and process technology of silicon, germanium and III-V devices and metal and optical interconnects for nanoelectronics, and high efficiency and low cost solar cells. He has supervised more than 90 doctoral students, 35 post doctoral scholars and has authored or co-authored over 800 technical papers. He is a Life Fellow of the IEEE. He received the Thomas Callinan Award from The Electrochemical Society in 2000, the IEEE Andrew Grove award in 2004, Inventor Recognition Award from MARCO/FCRP in 2007, the Technovisionary Award from the India Semiconductor Association in 2007 and the Semiconductor Industry Association Researcher of the Year Award in 2012. He is listed by ISI as one of the 250 Highly Cited Authors in his field.
This is an overview on new processing technologies required for continued scaling of leading edge and emerging semiconductor devices. The main drivers and trends affecting future semiconductor device scaling will be introduced in order to explain how these factors are influencing and driving process technology development. Process technologies currently under development or consideration for future device nodes will then be introduced with a focus on how they will be used for integrating future VLSI circuits and devices. The topics and technologies explored in this presentation include atomic layer deposition (ALD), atomic layer etching (ALE), selective deposition and etching, advanced surface preparation, EUV lithography, and self-aligned and multiple patterning schemes among others. A key point of this presentation will be to impart an understanding to attendees of how these advanced process technologies can be leveraged holistically to deliver power, performance, area and cost (PPAC) scaling for future VSLI devices. Real world examples of current and future integration schemes will be presented and explained so that attendees can understand how advanced process technologies will be used in future device manufacturing as well as what benefits and tradeoffs will be entailed in their use.
Robert Clark received his Ph.D. in Chemistry in 2000 from U.C. Irvine and holds B.S. and M.S. Chemistry degrees from Virginia Tech. He joined Air Products and Chemicals in 2000 where he worked as a Principal Research Chemist developing ALD High K and Metal Gate precursors. In 2006 he Joined Tokyo Electron at the TEL Technology Center, America (TTCA), LLC in Albany, New York and relocated to California in 2010. He is currently an elected Senior Member of the Technical Staff for Tokyo Electron U.S. He holds more than 35 issued U.S. patents and has authored or co-authored more than 100 publications and conference presentations including numerous invited presentations and papers.
Technology and design scaling at process nodes <20nm is becoming more challenging with every subsequent node. To overcome scaling roadblocks and maximize the performance benefits of scaling, circuit designers and process technologists work together through a process commonly known as Design-Technology Co-Optimization (DTCO). When DTCO first became necessary and popular, the MOSFET device dominated the cost and performance equations. However, in the era of multiple patterning and EUV lithography, the importance of the metal stack is quickly rising. This new paradigm has changed the face of DTCO and impacted the way we design integrated circuits.
This talk will discuss the evolution of DTCO from a device-centric regime to an interconnect-centric regime. It will introduce the current DTCO paradigm and its drivers, and then cover the resulting design implications in order of increasing complexity: from standard cells and bitcells to microprocessors and multi-core systems. Finally, the talk will conclude with a glimpse into the future and a prediction of where DTCO will go in years to come.
Dr. Brian Cline is a Principal Research Engineer in the Devices, Circuits, and Systems research group at Arm. His research interests include the IC design impact of emerging logic devices, memory devices, next generation lithography, and advanced packaging techniques. He also has interests in DTCO and EDA tools and methodologies. He received the B.S. degree in electrical engineering from the University of Texas at Austin, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan. From 2006-2010, he was a Graduate Fellow with the Semiconductor Research Corporation (SRC). In 2017, he was chosen as one of the recipients of the SRC Mahboob Khan Outstanding Industry Liaison award. He has published more than 25 papers, including several best paper award nominees, invited papers, and plenary sessions.
The role of 3D integration and packaging in semiconductor industry has transformed in recent years. Driven by markets diversification and front-end scaling challenges, 3D integration and packaging enable system scaling to fill the gaps left by system on chip (SoC) and system in package (SiP) and by More Moore (MM) and More than Moore (MtM). This short course covers the concepts behind this change. Starting from a brief introduction of 3D IC Packaging Trends, Stack Chips by Wire Bonding, PoP & CoC Interconnects, WLP, 3D IC Integration, High Bandwidth Memory (HBM), 2.5D IC Integration/Interposer, Supply Chains & business models for 2.5D/3D IC Integration, FOWLP & FOPLP, Thermal management and finally the new technology needed for the new role played by packaging, and the prospect on how the new system integration technology will help sustaining semiconductor industry’s future growth.
Chih Hang is Deputy Director of Exploratory 3D Program in TSMC R&D. He has worked in Taiwan and Singapore Semiconductor industry for near 30 years, covering areas including FEOL HKMG, silicide, to BEOL Cu low-k, and to far-back-end 3DIC and advanced packaging. Chih Hang obtained Master of Science degree from Illinois Institute of Technology (Chicago), has authored/co-authored for more than 200 technical papers, 20 US patents, and a book “ULSI Semiconductor Technology Atlas (Wiley 2003).” He serviced IEEE IPFA Chair in 2008, EDS Distinguished Lecturer (2007-2010), senior member since 2002, and received IEEE EDS Paul Rappaport Award in 2008.
In recent decades, STT-MRAM (spin-transfer torque magnetic RAM) has gained great attention due to its ideal memory properties such as non-volatility, fast write speed, high endurance, and strong retention. In particular, embedded MRAM technology is rapidly being developed for the commercialization. This short course will focus on overall MRAM technologies from principles to applications. We will talk about the key merits of STT-MRAM technology compared to other embedded non-volatile memories, and also will discuss basic concepts and operating mechanism of STT-MRAM in terms of device read and write operation. It is followed by giving explanation of its key technologies such as integration process, circuit design and electrical characterization. It will review the correlation between the technology and device characteristics, since it is important to understand the impact and influence of key technologies on the device performance. Finally, this talk will end with open discussion about technical challenges and hurdles such as small sensing margin, relative large switching current, trade-off between retention and switching current, and patterning difficulty.
Dr. Yoon Jong Song is VP of Process Architecture Team in Samsung Foundry, leading the development of STT-MRAM products embedded in 28nm logic platform. He is mainly involved in process integration, device characterization, and yield enhancement for eMRAM products. Since he joined Samsung Electronics in 1998, he has experience of developing various new memories such as FRAM, PRAM, and MRAM. His specialty is to integrate new memory devices and establish new characterization method and reliability standards. He has authored or co-authored over 100 publications related to new memory fields. He received Ph.D. degree in Materials Science and Engineering from Virginia Tech in USA in 1998
Power constraint of computing hardware has become a critical challenge for continued advancement of electronics. Power requirements ultimately limit bandwidth and thus the amount of data that can be processed. Recognizing this, a number of alternative logic switches has been investigated in the last decade. Some of them are functionally equivalent to today’s transistors, and could be a drop-in replacement, such as the Tunnel Field Effect Transistor (TFET) and Negative Capacitance Field Effect Transistor (NCFET), while some others are completely different, such as the Spin based switches. In addition, alternate channel materials such as two-dimensional semiconductors have attracted a lot of attention. In this presentation, I shall briefly summarize the main motivations for these devices in terms of their principle of operation. All these devices pose the challenge of introducing new materials in the CMOS production line. Compatibility with large scale integration might ultimately decide their eventual adoption.
S. Salahuddin is a professor of Electrical Engineering and Computer Sciences at the University of California Berkeley. His work has focused mostly on conceptualization and exploration of novel device physics for low power electronic and spintronic devices. Salahuddin has received the Presidential Early Career Award for Scientist and Engineers (PECASE). Salahuddin also received a number of other awards including the NSF CAREER award, the IEEE Nanotechnology Early Career Award, the Young Investigator Awards from the Air Force Office of Scientific Research (AFOSR) and the Army Research Office (ARO) and best paper awards from IEEE Transactions on VLSI Systems and from the VLSI-TSA conference. In 2012, Applied Physics Letters (APL) highlighted two of his papers among 50 most notable papers among all areas published in APL within 2009-2012. Salahuddin is a co-director of the Berkeley Device Modeling Center (BDMC) and Berkeley Center for Negative Capacitance Transistors (BCNCT). Salahuddin is also a co-director of ASCENT, one of the six centers of the JUMP initiative sponsored by SRC/DARPA. He served on the editorial board of IEEE Electron Devices Letters (2013-16) and was the chair the IEEE Electron Devices Society committee on Nanotechnology (2014-16). Salahuddin is a Fellow of IEEE.
In the last decade, flash memory array has been most aggressively scaled down in the semiconductor industry because NAND architecture is very simple concept for its basic functionality and pattern layout. It was NAND architecture that double patterning, quadro patterning, multi-level cell and three-dimensionally arrayed memory cell were implemented for the manufacturing technology relatively earlier than other device architecture. In this tutorial, history of three-dimensionally arrayed flash memory technology is introduced and its basic device concept and process technology are explained. Finally the device and process technology challenges are discussed for the future three-dimensionally arrayed flash memory.
Ryota Katsumata received the Ph.D. in Science and Engineering, University of Tsukuba in 1994. In 1994, he joined Toshiba corp. R&D center USLI research Lab, where he researched Fluorinated silicon dioxide (FSG) and its plasma CVD process. From 1997 to 2000, he joined to DRAM development alliance (DDA) project for IBM, Siemens and Toshiba in East Fishkill, NY. In 2007, his team in which he is responsible to lead device and integration engineer innovated BiCS flash technology and presented its concept in VLSI symposium 2007. Currently, he is responsible to future flash BiCS technology development as a director in Toshiba Memory Corporation.