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The following press materials are available for pre-conference publicity for the 2018 Symposia on VLSI Technology & Circuits

Press Releases


VLSI Symposia 2018 Tip Sheet (English)

VLSI Symposia 2018 Lead release (English)

VLSI Symposia 2018 Theme release (English)

VLSI Symposia 2018 Call for Papers (English)

VLSI Symposia 2018 Lead Release (Chinese)

VLSI Symposia 2018 Tip Sheet (Chinese)

VLSI Symposia 2018 Tip Sheet Technical Terms (Chinese)

VLSI Symposia 2018 Lead Release (Japanese)

VLSI Symposia 2018 Tip Sheet (Japanese)

VLSI Symposia 2018 Tip Sheet Technical Terms (Japanese)

VLSI Symposia 2018 Lead Release (Korean)

VLSI Symposia 2018 Tip Sheet (Korean)

VLSI Symposia 2018 Tip Sheet Technical Terms (Korean)

 

 

 

 

Images


Hilton Hawaiian Village Venue

2018 VLSI Symposium Technology logo

2018 VLSI Symposium Circuits logo

2018 VLSI Symposium Theme

 

Paper T6-1True 7nm Platform Technology Featuring Smallest FinFET and Smallest SRAM Cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break” WC Jeong, et al., Samsung Electronics

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Paper T6-2, “Nanosecond Laser Anneal for BEOL Performance Boost in Advanced FinFETs” R.T.P. Lee, et al., GLOBALFOUNDRIES)

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Paper T6-3 “From Memory to Sensor: Ultra-Low Power and High Selectivity Hydrogen Sensor Based on ReRAM Technology” Z. Wei, et al., Panasonic Corporation & National Institute of Advanced Industrial Science and Technology, Japan

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Paper T6-4 “Demonstration of Ultra-Low Voltage pSTT-MRAM designed for compatibility with 0x node embedded LLC applications” G. Jan et al., TDK/Headway Technologies

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Paper T9-1, “10μW/cm2-Class High Power Density Silicon Thermoelectric Energy Harvester Compatible with CMOS-VLSI Technology” M. Tomita et al., Waseda Univ., Osaka Univ., Shizuoka Univ. and AIST Japan

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Paper T12-1 “All-Electrical Control of a Hybrid Electron Spin/Valley Quantum Bit in SOI CMOS Technology” L. Hutin, et al., CEA LETI, CEA INAC and CNRS

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Paper T15-5, “InGaAs-on-Insulator MOSFET Featuring Scaled Logic Devices and Record RF Performance” C.B. Zota, et al., IBM, Fraunhofer IAF.

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Paper T17.1 “Embedded STT-MRAM in 28-nm FDSOI Logic Process for Industrial MCU/IoT Application” Y. K. Lee, et al., Samsung Electronics

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Paper T18-4 “High Performance Mobile SoC Productization with Second-Generation 10nm FinFET Technology and Extension to 8-nm Scaling” Y. Yuan, et al., Qualcomm, Samsung

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Paper 19-3 “High Endurance Self-Heating OTS-PCM Pillar Cell for 3D Stackable Memory”, C.W. Yeh, et al., Macronix, IBM

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Paper T20-2 “First demonstration of vertically stacked Gate-All-Around highly-strained Germanium nanowire p-FETs” E. Capogreco, et al., imec

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Paper C3-2 “An 113dB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TX”  T. Wang, et al., Toshiba

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Paper C5-2 “A 112Gb/s PAM4 Wireline Receiver Using a 64-way Time-Interleaved SAR ADC in 16nm FinFET”  J. Hudner, et al., Xilinx

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Paper C7-1 “A Two-Tap NIR Lock-In Pixel CMOS Image Sensor with Background Light Cancelling Capability for Non-Contact Heart Rate Detection” C. Cao, et al., Shizuoka University, Brookman Technology, Chiba University

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Paper C8-1 “Logic Process Compatible 40nm 16Mb, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, sub-μA Sensing Resolution, and 17.5nS Read Access Time”  Y.-C. Shih, et al., TSMC

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Paper C9-1 “A 12-bit 31.1uW 1MS/s SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4dB SFDR using 256fF Sampling Capacitance”  J. Shen, et al., Analog Devices

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Paper C11-1 “A CMOS Molecular Clock Probing 231.061-GHz Rotational Line of OCS with Sub-ppb Long-Term Stability and 66-mW DC Power”  C. Wang, et al., MIT

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Paper C12-1 “A 0.8V 82.9μW In-ear BCI Controller System with 8.8 PEF EEG Instrumentational Amplifier and Wireless BAN Transceiver” J. Lee, et al., KAIST, MIT

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Paper C13-1 “Navion: A Fully Integrated Energy-Efficient Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones” A. Suleiman, et al., MIT

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Paper C16-4 “220mV-900mV 794/584/754 Gbps/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14nm Tri-gate CMOS” S. Satpathy, et al., Intel

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Paper C20-3 “A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 dB EVM at 1024 QAM in 28nm CMOS” N. Markulic, et al., imec, Vrije Universiteit Brussel

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Paper C22-1 “A 1mW -101dB THD-N Class-AB High-Fidelity Headphone Driver in 65nm CMOS” N. Mehta, et al., University of California, Berkeley, TU Delft

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Paper C24-1 “A 4096-neuron 1M-synapse 3.8pJ/SOP Spiking Neural Network with On-chip STDP Learning and Sparse Weights in 10nm FinFET CMOS” G. Chen, et al., Intel

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PRESS REGISTRATION


Registration at the 2018 Symposia on VLSI Technology & Circuits is complimentary for the press. Whether you would like to do a news story, conference preview or an in-depth exploration of a particular technology, please contact one of us for the additional information or interviews you may need.

Register Now

If you plan to attend, please contact us; or print out the registration page with your contact information, write “Press” on it, and fax or mail it to Conference Manager Phyllis Mahoney, 19803 Laurel Valley Place, Montgomery Village, MD 20886, USA; tel. +1-301-527-0900, ext. 2; fax +1 527-0994. Phyllis also can be reached by email with any registration/attendance questions at phyllism@widerkehr.com.

Be prepared to show a business card when you arrive at the Symposia.

Editor Contact


Chris Burke
Media Relations Director
+1 919-872-8172
chris.burke@btbmarketing.com

Phyllis Mahoney
Conference Manager
+1 301-527-0900
phyllism@widerkehr.com