Requirements for both the 2017 Symposia on VLSI Technology and the 2017 Symposia on VLSI Circuits Best Student Paper Award

Both the Symposium on VLSI Technology and the Symposium on VLSI Circuits recognize outstanding student papers with a Best Student Paper Award. The awards were established in 2004 to promote student research and support the development of future leaders in the fields of VLSI Technology and VLSI Circuits. Award recipients are selected based on the quality of their written papers and the quality of their presentations at the Symposia. Award recipients receive a monetary prize and certificate, presented at the opening session of the Symposium held in the following year. Award recipients’ travel expenses and registration fees for the Symposium held in the following year are covered by the Symposia. Candidates for the awards must be enrolled as full-time students at the time of paper submission, must be the leading author and the presenter of their papers, and must indicate at submission that their papers should be considered for the award.

VLSI BSPA verification form

As a candidate for VLSI BSPA, student author needs to fill out “Verification Form for VLSI Student Paper” including Professor/Industrial supervisor sign.
Then it is needed to be sent to VLSI secretariat (vlsisymp@jtbcom.co.jp) in scanned pdf form for accepted student papers by Apr. 20th.

Former Best Student Paper Award Winners

Past Technology Paper Winners

Recipient: Cimang Lu

Paper:Design and Demonstration of Reliability-Aware Ge Gate Stacks with 0.5 nm EOT

Authors: Cimang Lu, Choong Hyun Lee, Tomonori Nishimura and Akira Toriumi

Affiliation:The University of Tokyo, JST-CREST

Recipient: Heng Wu

Paper: Ge CMOS: Breakthroughs of nFETs ( Imax= 714 mA/mm, gmax= 590 mS/mm) by Recessed Channel and S/D

Authors: Heng Wu, Mengwei Si, Lin Dong, Jingyun Zhang, Peide Ye

Affiliation: Purdue University

Recipient: ChoongHyun Lee

Paper: Enhancement of High-Ns Electron Mobility in Sub-nm EOT Ge n-MOSFETs

Authors: ChoongHyun Lee, Cimang Lu, Toshiyuki Tabata, Tomonori Nishimura, Kosuke Nagashio, and Akira Toriumi

Affiliation: The University of Tokyo

Recipient: Rui Zhang

Paper: High Mobility Ge pMOSFETs with 0.7 nm Ultrathin EOT using HfO2/Al2O3/GeOx/Ge Gate Stacks Fabricated by Plasma Post Oxidation

Authors: Rui Zhang, Po-Chin Huang, Noriyuki Taoka, Mitsuru Takenaka and Shinichi Takagi

Affiliation: The University of Tokyo

Recipient: Jiale Liang

Paper: A 1.4μA Reset Current Phase Change Memory Cell with Integrated Carbon Nanotube Electrodes for Cross-Point Memory Application

Authors: Jiale Liang, Rakesh Gnana David Jeyasingh, Hong-Yu Chen, and H. -S. Philip Wong

Affiliation: Stanford University

Recipient: Laurent Brunet

Paper: New Insight on VT stability of HK/MG stacks with scaling in 30nm FDSOI technology

Authors: Laurent. Brunet*+, X. Garros, M. Cassé, O. Weber, F. Andrieu, C. Fenouillet-Béranger, P. Perreau, F. Martin, M. Charbonnier, D. Lafond, C. Gaumer*, S. Lhostis*, V. Vidal, L. Brévard, L. Tosti, S. Denorme*, S. Barnola, J.F. Damlencourt, V. Loup, G. Reimbold, F. Boulanger, O. Faynot, A. Bravaix

Affiliation: 1CEA-LETI, * STMicroelectronics, +IM2NP

Recipient: Gregory Bidal

Paper: High velocity Si-nanodot: a candidate for SRAM applications at 16nm node and below

Authors: Gregory Bidal1,2, Frederic Boeuf1, Stephane Denorme1, Nicolas Loubet1, Jean Luc Huguenin1,2, Pierre Perreau3, Dominique Fleury1,2, François Leverd1, Sebastien Lagrasta1, Sebastien Barnola3, Thierry Salvetat3, Bastien Orlando1, Remi Beneyton1, Laurent Clement1, Roland Pantel1, Stephane Monfray1, Gerard Ghibaudo2 and Thomas Skotnicki1

Affiliation: 1STMicroelectronics, 2IMEP, Minatec INPG, 3CEA-LETI/Minatec

Recipient: Nishant Patil and Albert Lin

Paper: Integrated Wafer-Scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures

Authors: Nishant Patil, Albert Lin, Edward R. Myers, H.-S. Philip Wong, and Subhasish Mitra

Affiliation: Stanford University

Recipient: Mohan V. Dunga

Paper: BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design

Authors: Mohan V. Dunga1, Chung-Hsun Lin1, Darsen D. Lu1, Weize Xiong2, C. R. Cleavelin2, P. Patruno3, Jiunn-Ren Hwang4, Fu-Liang Yang4, Ali M. Niknejad1 and Chenming Hu1

Affiliation: 1University of California, Berkeley, 2Texas Instruments Inc., 3SOITECH, 4Taiwan Semiconductor Manufacturing Company (TSMC)

Recipient: Hyunjin Lee

Paper: Sub-5nm All-Around Gate FinFET for Ultimate Scaling

Authors: Hyunjin Lee, Lee-Eun Yu, Seong-Wan Ryu, Jin-Woo Han, Kanghoon Jeon, Dong-Yoon Jang, Kuk-Hwan Kim, Jiye Lee, Ju-Hyun Kim, Sang Cheol Jeon*, Gi Seong Lee*, Jae Sub Oh*, Yun Chang Park*, Woo Ho Bae*, Hee Mok Lee*, Jun Mo Yang*, Jung Jae Yoo*, Sang Ik Kim* and Yang-Kyu Choi

Affiliation: Korea Advanced Institute of Science and Technology, *Korean National Nanofab Center

Recipient: Chien-Tai Chan

Paper: Investigation of Post-NBTI Stress Recovery in pMOSFETs by Direct Measurement of Single Oxide Charge De-Trapping

Authors: Chien-Tai Chan, Huan-Chi Ma, Chun-Jung Tang and Tahui Wang

Affiliation: National Chiao-Tung University

Recipient: Sunjung Kim

Paper: Engineering of Voltage Nonlinearity in High-K MIM Capacitor for Analog/Mixed-Signal ICs

Authors: Sunjung Kim1, Byung Jin Cho1, Ming-Fu li1,2, Shi-Jin Ding1, Ming Bin Yu2, Chunxiang Zhu1, Albert Chin3, and Dim-Lee Kwong4

Affiliation: 1National University of Singapore, 2Institute of Microelectronics (IME), Singapore, 3National Chiao Tung University, 4University of Texas, Austin

Past Circuits Paper Winners

Recipient: Abishek Manian

Paper: A 40-Gb/s 9.2-mW CMOS Equalizer

Authors: A. Manian and B. Razavi

Affiliation: University of California, Los Angeles

Recipient: Maryam Tabesh

Paper: A Power-Harvesting Pad-Less mm-Sized 24/60GHz Passive Radio with On-Chip Antennas

Authors: Maryam Tabesh, Mustafa Rangwala*, Ali M. Niknejad and Amin Arbabian*

Affiliation: University of California, Berkeley and *Stanford University

Recipient: Yingzhe Hu

Paper: A Fully Self-Powered Hybrid System Based on CMOS ICs and Large-Area Electronics for Large-Scale Strain Monitoring

Authors:Yingzhe Hu, Liechao Huang, Josue Sanz Robinson, Warren Rieutort-Louis, Sigurd Wanger, James C. Sturm, Naveen Verma

Affiliation: Princeton University, USA

Recipient: Jun Won Jung

Paper: A 25-Gb/s 5-mW CMOS CDR/Deserializer

Authors: Jun Won Jung and Behzad Razavi

Affiliation: University of California, Los Angeles, CA, USA

Recipient: Chintan Thakkar

Paper: A 10Gb/s 45mW Adaptive 60GHz Baseband in 65nm CMOS

Authors: Chintan Thakkar1, Lingkai Kong1, Kwangmo Jung1, Antoine Frappé2, and Elad Alon1

Affiliation: 1University of California, Berkeley, USA & 2Institut Supérieur de l’Electronique et du Numérique, France

Recipient: Dajiang Zhou

Paper: A 530Mpixels/s 4096×2160@60fps H.264/AVC High Profile Video Decoder Chip

Authors: Dajiang Zhou1, Jinjia Zhou1, Xun He1, Ji Kong2, Jiayi Zhu2, Peilin Liu2, and Satoshi Goto1

Affiliation: 1Waseda University, Japan & 2Shanghai Jiao Tong University, China

Recipient: Zhengya Zhang

Paper: A 47 Gb/s LDPC Decoder with Improved Low Error Rate Performance

Authors: Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic

Affiliation: University of California, Berkeley, USA

Recipient: Jason Hu

Paper: A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC using Dynamic Residue Amplification

Authors: Jason Hu, Noam Dolev and Boris Murmann

Affiliation: Stanford University, USA

Recipient: Minjae Lee

Paper: A 9b, 1.25ps Resolution Coarse-Fine Time-to- Digital Converter in 90nm CMOS that Amplifies a Time Residue

Authors: Minjae Lee and Asad A. Abidi

Affiliation: University of California, Los Angeles, USA

Recipient: Koon-Lun Jackie Wong

Paper: A 5-mW 6-Gb/s Quarter-Rate Sampling receiver with a 2-Tap DFE Using Soft Decisions

Authors: Koon-Lun Jackie Wong1, Alexander Rylyakov2, and Chih-Kong Ken Yang1

Affiliation: 1University of California, Los Angeles, USA & 2IBM T. J. Watson Research Center, USA

Recipient: Antonio Liscidini

Paper: A 0.13 um CMOS Front-End for DCS1800/UMTS/ 802.11b-g with Multi-band Positive Feedback Low Noise Amplifier

Authors: Antonio Liscidini, Massimo Brandolini, Davide Sanzogni, and Rinaldo Castello

Affiliation: University of Pavia, Italy

Recipient: Timothy O. Dickson

Paper: A 2.5-V, 40-Gb/s Decision Circuit Using SiGe BiCMOS Logic

Authors: Timothy O. Dickson1, Rudy Beerkens2, and Sorin P. Voinigescu1

Affiliation: 1University of Toronto, Canada & 2STMicroelectonics, Canada

VLSI Technology Technical Program Committee

Chair: Meishoku Masahara
Co-Chair: Chorng-Ping Chang

VLSI Circuits Technical Program Committee

Chair: Makoto Ikeda
Co-Chair: Ken Chang