Short Course: Advanced Wirelines Techniques
Over the past decade, wireline data rates have doubled about every four years to keep pace with aggregate system bandwidth requirements. Electrical signaling standards for networking, telecom and storage applications – including Ethernet and OIF-CEI – tend to be the first to define the path to increase line rates. Today, links up to 28Gb/s/lane are being widely deployed. Meanwhile, standards for 50-56Gb/s are being defined, and we are seeing early demonstrations of transceivers and components meeting this bandwidth. This presentation will provide an overview of standards, circuit architectures and design tradeoffs for 28-56Gb/s links. It will start by providing a summary of recent data rate scaling trends and standards for 28-56Gb/s and show where wireline is used in high-performance systems. Next it will describe the key tradeoffs for increasing aggregate bandwidth, including power, channel quality and process technology capability. Then it will discuss how recent standards have balanced these tradeoffs, and describe the implications for circuit architecture and design, including equalization, clocking, modulation and error correction. Finally we will summarize the existing design data points from industry and academic publications for 28-56Gb/s.
Frank leads the I/O Circuit Technology group within Advanced Design at Intel in Hillsboro, Oregon, where he is a Principal Engineer. His group develops the first wireline I/O circuits for each new CMOS process technology. From 2003 until 2011 he was a member of the Signaling Research group in Intel’s Circuit Research Lab where his work focused on high-speed and low-power transceivers, clocking and on-die measurement techniques. Prior to joining Intel, Frank received the BS, MS, and PhD degrees in electrical engineering from Stanford University. Frank is the chair of the ISSCC Wireline Subcommittee and previously served as an Associate Editor for TCAS-I. He is a past recipient of the ISSCC Jack Kilby Award and TCAS Darlington Best Paper Award and is an IEEE Distinguished Lecturer.
High speed serial I/Os continue to be pushed to higher line rates for every new generation of systems including servers, switches, and routers, to enable the scaling of data centers fueled by a world that is becoming increasingly connected and digital. To address the bandwidth needs of these future systems, a new generation of chip-to-chip electrical serial links running at 25-28Gb/s data rates are now readily available in the industry, and have been standardized in various standard bodies such as Ethernet and Fiber Channel. This talk will focus on design considerations of low power and high density CMOS transceivers for backplane electrical links running at 28Gb/s and beyond. At these speeds, a high quality backplane channel exhibits more than 30dB of loss and can be reflective, requiring the use of specific channel equalization techniques, and in some cases forward error correction in order to operate the links at sufficiently low BER. While NRZ continued to remain the mainstream signaling for backplane links, Ethernet 802.3bj standard included a PHY clause for PAM4 signaling to enable the use of lower cost legacy 10Gb/s class backplanes.
Dr. Mounir Meghelli received the M.S. degree in electronics and automatics from the University of Paris Orsay in 1992 and the Engineering degree in Telecommunication from the ENST-Paris, in 1994. He received his Ph.D. degree from the University of Paris VI after a 4 year research program with the CNET France Telecom Research Center, working on the design of high-speed ICs for optical communications in GaAs and InP HBT technologies.
From 1998 to 2005, he joined the IBM T.J. Watson Research Center as a Research Staff Member working on the design of high frequency ICs in SiGe BiCMOS and CMOS technologies for wireline and wireless applications. From 2006 to 2011, he joined the IBM Server and Technology Group where he held a position of Senior Technical Staff Member position leading the design of advanced serial links for storage, networking and server applications. He is currently managing the Mixed Signal Communication IC Design group at the IBM T.J. Watson Research Center.
In order to increase data rates to 100-, 200- and 400-Gb/s on a single wavelength or a single copper channel, higher orders of modulation will be required. This could be PAM-4 or PAM-8 in a baseband system or QAM-16 or QAM-64 in coherent systems when optical in-phase and quadrature carriers are available. The increased throughput, coupled with strict power requirements, means that as the data rate is going up, the transceiver power is required to drop. Therefore ADCs needed for these receivers must be faster, have higher resolution, less noise and dissipate less power than for previous solutions. This Short Course will review the requirements of PAM-x / QAM-X systems in both backplane and optical links. Error sources of the ADCs will be discussed in the context of the system and their impact on overall bit-error-rate performance with the aim of determining exactly what is needed and what is mere “specsmanship.” This is essential as any over-designed aspect of the system will hurt the power budget. Pros and Cons of various architectural choices will be considered and various calibration strategies will be discussed. An example ADC will be presented to illustrate the concepts in more concrete detail.
Dr. Aaron Buchwald has 34 years experience in the field of analog integrated circuit design. He is currently a Senior Technical Director at InPhi Corporation. Before that he was Fellow at Entropic Communications after their acquisition of Mobius Semiconductor, where he was CEO and founder. Prior to Mobius, Dr. Buchwald worked at Broadcom. Dr. Buchwald is currently an Adjunct Professor at the Hong Kong University of Science and Technology (HKUST) where he was previously an Assistant Professor. In his early career, Dr. Buchwald spent two years as an analog IC designer at Siemens in Munich Germany. Prior to that, he spent four years at Hughes Aircraft Company in El Segundo, CA. Dr. Aaron Buchwald was born in Ames, Iowa and received a BSEE from the University of Iowa, Iowa City, Iowa, and an M.S. and Ph.D. from the University of California, Los Angeles. He is co-author of the book Integrated Fiber-Optic Receivers. He has taught professional short-courses and tutorials on data converters and serial transceivers. He served on the Data Converters sub-committee at ISSCC and is an Associate Editor for JSSC.
With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal will eventually be required in wireline chip-to-module or chip-to-chip communications. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient transceiver is needed. In conventional transceivers, the power consumption of the equalizer and the clock and data recovery (CDR) circuit are dominant, so reducing their power consumption has been the most challenging design issue. In this presentation, I will talk the most power efficient 56-Gb/s transceiver that has a baud-rate sampling with a new phase detection scheme and a look-ahead DFE as well as a power-efficient transmitter.
Hisakatsu Yamaguchi received the graduate degree in electrical engineering from the Tokyo University of Science, Chiba, Japan, and the M.S. degree in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1994, and 1996, respectively. In 1996, he joined Fujitsu Laboratories. Ltd., Kawasaki, Japan, where he has been engaged in research on DRAMs with high-speed I/Os and has been responsible for developing MPEG4 Codec ICs. He is currently working on developing high-speed I/Os for high-end servers and super-computers. He has served on the Technical Program Committees of ISSCC from 2012 to 2016.
Demand for data communication in cloud datacenters is projected to grow exponentially in the next few years. Optical interconnects based on silicon photonics (SiPh) have emerged as a scalable technology satisfying this growing need for interconnect bandwidth at progressively shorter link distances. In this talk, we will give an overview of recent progress in the development of a SiPh platform enabling 56G NRZ lane rates. We will compare various options for realizing low-voltage 56G silicon integrated optical modulators and highlight recent progress in developing highly responsive 56G Ge waveguide photodetectors on silicon. Next, we will discuss CMOS-SiPh co-design opportunities to optimize electro-optic link performance, which we will illustrate with a recent example of a 28nm CMOS-SiPh ring-based NRZ transmitter operating at up to 50Gb/s. Finally, we will review a recent proof-of-concept demonstration of a hybrid CMOS-SiPh 4x20G transceiver with integrated wavelength division multiplexing. To conclude, we will provide an outlook on future trends.
Joris Van Campenhout is program director of the Optical I/O industry-affiliation program at imec (Belgium), which targets the development of a scalable and industrially viable optical-interconnect technology based on silicon photonics. Prior to joining imec, he was a post-doctoral researcher at IBM’s TJ Watson Research Center (USA), where he developed silicon electro-optic switches for chip-level reconfigurable optical networks. He obtained a PhD degree in Electrical Engineering from Ghent University (Belgium) in 2007, for his work on hybrid integration of electrically driven III-V microdisk lasers on silicon photonic waveguide circuits. Joris holds 4 patents and has authored or co-authored over 100 papers in the field of silicon integrated photonics. He is a member of IEEE and OSA.
Today’s chips suffer from a large mismatch between internal computational capability and inability of the I/O to deliver the required data, both in terms of energy-cost and bandwidth-density. Silicon-photonic technology is well positioned to overcome these two fundamental difficulties of electrical links, but proper integration strategies need to be applied to preserve its advantages.
In this talk we’ll present the latest results on the integration of silicon-photonic interconnects in several fabrication processes. These include world’s first microprocessor communicating to the outside world with monolithically integrated Si-Photonic devices, as well as the first demonstration of photonics in a bulk CMOS process. We’ll also illustrate some critical aspects of this technology that need to be addressed from integration, circuits and systems side, in order to realize the full energy-efficiency and bandwidth-density potential of this technology.
Vladimir Stojanovic is an Associate Professor of Electrical Engineering and Computer Science at University of California, Berkeley. His research interests include design of integrated systems with CMOS and emerging devices like NEM relays and silicon-photonics. He is interested in process integration, circuit and system design for a range of applications – from energy-efficient computing to high-density communication and sensing.
Vladimir received his Ph.D. in Electrical Engineering from Stanford University in 2005, and the Dipl. Ing. degree from the University of Belgrade, Serbia in 1998. He was also with Rambus, Inc., Los Altos, CA, from 2001 through 2004 and with MIT as Associate Professor from 2005-2013. He received the 2006 IBM Faculty Partnership Award, and the 2009 NSF CAREER Award as well as the 2008 ICCAD William J. McCalla, 2008 IEEE Transactions on Advanced Packaging, and 2010 ISSCC Jack Raper best paper awards. He was an IEEE Solid-State Circuits Society Distinguished Lecturer for the 2012-2013 term.